DSP design flows in FPGAs: Strategies for designing DSP applications for FPGAs

Yankin Tanurhan, Vlad Dinkevich, Manish Dharod, and Shafi Syed, Actel Corp.
(04/05/2006 6:01 PM EDT), EE Times

Introduction
Digital signal processing (DSP) occurs in communications, audio, and multimedia devices, imaging and medical equipment, smart antennas, automotive electronics, MP3 players, radar and sonar, and barcode readers, to name but a few. According to market research firm Forward Concepts' November 1, 2005 DSP/Wireless Market Bulletin, the estimated market for programmable DSP chips should exceed $8B in 2005.

DSP platforms
DSP algorithms can be implemented in many different ways. The most popular being as follows:

General-purpose microprocessors (e.g. Pentium) and general-purpose microcontrollers (e.g. 8051) can run DSP algorithms of arbitrary complexity.
Programmable DSP chips or DSP microprocessors (uP). The internal structure of DSP uPs is optimized to run many DSP algorithms much faster and more efficiently. For example, the DSP chips have one or more built-in fast hardware multiplier-accumulator (MAC) to perform MAC operations DSP algorithms make heavy use of.
FPGA. An FPGA can be configured to run a particular DSP algorithm, thereby dedicating FPGA resources to particular DSP tasks. Also, the FPGA can run hundreds of MAC units in parallel. As a result, the performance may far exceed that of DSP uPs.
ASIC. An ASIC offers even higher levels of "dedication" than the FPGA. ASICs are the champion when comparing performance per square millimeter of silicon. It is important to note, however, that the gap between the ASIC and the FPGA tends to narrow as the FPGA grows in size (e.g. larger than 1 million gates).

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