English
PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
You are here:
DSC 1.2b Decoder
The DSC 1.2b Decoder is an efficient video decompression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for low power consumption and compact size, this IP delivers real-time, visually lossless stream decoding for high-bandwidth display applications. It is compatible with several transport standards, including MIPI DSI-2 1.1, DisplayPort 1.4, and HDMI 2.1. The decoder supports all DSC 1.2b coding schemes, such as MMAP, BP, MPP, and ICH, and handles multiple color formats including YCbCr 4:4:4, 4:2:2, 4:2:0, and RGB. Additionally, the core is cost-effective and scalable, meeting the demands of higher resolution or higher frame rate displays, and supports up to 4-slice decoding.
View DSC 1.2b Decoder full description to...
- see the entire DSC 1.2b Decoder datasheet
- get in contact with DSC 1.2b Decoder Supplier
Block Diagram of the DSC 1.2b Decoder IP Core
DSC IP
- VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC (Display Stream Compression) 1.2b Video Decoder
- ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- VESA DSC 1.2b Encoder for Xilinx FPGAs
- VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs