English
Analysis: Altera jumps to 40 nm with Stratix IV
By BDTI
June 05, 2008 -- dspdesignline.com
Altera has unveiled its next-generation high-performance FPGA family, the Stratix IV, and announced that the family will be fabbed in a 40 nm TSMC process. The new Stratix IV chip family will include 12 members: six GX devices, and six E devices. GX chips have from 8-48 high-speed serial transceivers, while the E devices have no transceivers but more memory and more DSP-oriented features. The highest capacity Stratix IV chips will have roughly double the logic capacity of the biggest Stratix III chips—up to 680K logic elements. The new chips will also include up to 22.4 Mbits of internal RAM. Pricing has not yet been announced.
June 05, 2008 -- dspdesignline.com
Altera has unveiled its next-generation high-performance FPGA family, the Stratix IV, and announced that the family will be fabbed in a 40 nm TSMC process. The new Stratix IV chip family will include 12 members: six GX devices, and six E devices. GX chips have from 8-48 high-speed serial transceivers, while the E devices have no transceivers but more memory and more DSP-oriented features. The highest capacity Stratix IV chips will have roughly double the logic capacity of the biggest Stratix III chips—up to 680K logic elements. The new chips will also include up to 22.4 Mbits of internal RAM. Pricing has not yet been announced.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Altera Stratix IV User Guide Lite
- Altera courts ASIC designers with block-based Stratix PLD
- Analysis and Summary on Clock Generator Circuits and PLL Design
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
- Design-Stage Analysis, Verification, and Optimization for Every Designer