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20 Most Popular Articles
Updated: Sun, 29 Jun 2025 01:00:01 +0200
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How to design secure SoCs, Part II: Key Management Have you ever wondered how secure critical systems, like medical devices, aerospace systems or autonomous cars, really are when it comes to data protection? One point of the answer lies in effective and robust key management. |
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MIPI in FPGAs for mobile-influenced devices A new wave of applications for mobile-influenced devices, using technology initially designed for mobile devices, demand high-resolution, high-frame-rate streaming data from vision sensors, especially with the rise of AI inference models performing real-time scene and object classification. |
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Optimizing 16-Bit Unsigned Multipliers with Reversible Logic Gates for an Enhanced Performance |
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Automating Hardware-Software Consistency in Complex SoCs Engineering teams must coordinate across hardware and software domains as system-on-chip (SoC) designs scale in complexity. Designers must verify that register definitions remain accurate and synchronized throughout the development cycle. |
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How NoC architecture solves MCU design challenges As MCUs take on greater workloads, the conventional bus-based interconnects that once sufficed now limit performance and scalability. Adding artificial intelligence (AI) accelerators, machine learning technology, reconfigurable logic, and secure processing elements demands a more advanced on-chip communication infrastructure. |
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Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem The rapid growth of mobile computing, AI, and Automotive technologies is driving demand for faster, more efficient, and highly reliable memory with higher capacity |
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How to Design Secure SoCs: Essential Security Features for Digital Designers In this comprehensive guide, we will explore the essential components of secure SoC design and explain how a robust security subsystem can protect sensitive assets throughout the chip’s lifecycle. Additionally, we will dive into how KiviCore’s specialized consultancy services can help ASIC and SoC design companies navigate the complex security landscape, ensuring the creation of secure and reliable chips that meet the rigorous demands of industries like IoT, data processing, consumer, telecommunication and beyond. |
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System level on-chip monitoring and analytics with Tessent Embedded Analytics In the rapidly evolving landscape of System on Chip (SoC) development, the demand for effective debugging and optimization is becoming increasingly prevalent. As SoCs grow in complexity, incorporating diverse architectures and managing varied workloads, the necessity for efficient validation, debugging, and performance optimization intensifies. |
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What tamper detection IP brings to SoC designs The growing complexity and frequency of security threats facing organizations across the globe has transformed opinion about what’s needed to keep devices secure. Modern system-on-chips (SoCs) take a ‘Zero Trust’ approach, assuming that no user, device or application is inherently trustworthy. In parallel to this approach, complementary solutions, including anti-tamper measures, are increasingly importan |
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RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware RISC-V has been a hot topic in the semiconductor industry for several years now, and for good reason. As an open standard ISA alternative to traditional processor architectures like ARM and x86, it carries a huge weight of expectation, but also significant hurdles to widespread adoption. It’s clear that RISC-V is making progress, but the road ahead isn’t smooth. |
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Understanding MACsec and Its Integration MACsec, as defined by the IEEE 802.1AE standard, provides protection for traffic passing over Layer 1 and Layer 2 links. It is designed to prevent a range of security threats, including man-in-the-middle attacks, pasive wiretapping, impersonation, and replay attacks. By applying protection at the data link layer, MACsec ensures that all communication between devices on the same network segment is secure. |
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Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development. |
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The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know Innosilicon Technology Inc. 97 E Brokaw Rd #210, San Jose, CA 95112 For more information, contact sales@innosilicon.com www.innosilicon.com |
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Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency This paper aims to provide a comprehensive understanding of density issues, and the methodologies used to perform effective density checks in VLSI layout design. |
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Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation In this paper we introduce Nexus: a lightweight Python framework designed to easily build and manage LLM-based MASs. Nexus introduces the following innovations: (i) a flexible multi-supervisor hierarchy, (ii) a simplified workflow design, and (iii) easy installation and open-source flexibility: Nexus can be installed via pip and is distributed under a permissive open-source license, allowing users to freely modify and extend its capabilities. |
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How the Ability to Manage Register Specifications Helps You Create More Competitive Products The semiconductors business is incredibly competitive, with dynamic end markets and constant shifts in leading products and vendors. It takes excellence on many fronts to succeed, far more than I can cover in a single blog post. Thus, I’m going to focus on one particular aspect of developing competitive IP and system-on-chip (SoC) products: the ability to manage your register specifications and automate the process of turning them into silicon. |
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EAVS - Electra IC Advanced Verification Suite for RISC-V Cores |
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Why RISC-V is a viable option for safety-critical applications This article examines the technical advantages and considerations of implementing RISC-V in safety-critical environments. |
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Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices In this blog post, we shall explore the methodology of 3D reconstruction on the multi-view object scenes, used for volumetric object dimensioning in autonomous robots. We shall also detail the steps of capturing data streams, generating object point clouds, reconstructing 3D point clouds through local and global registration algorithms, and calculating object dimensions in 3D. The results will be presented at the end. |
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What is JESD204B? Quick summary of the standard The JESD204B Standard enables the establishment of high-speed serial links between a Controller and ADC and DAC converters with Deterministic Latency. JESD204B was first published in July 2011 and was the first JESD204 standard version to describe the deterministic latency mechanism. |
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