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20 Most Popular News
Updated: Thu, 05 Jun 2025 01:00:02 +0200
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RISC-V International Promotes Andrea Gallo to CEO RISC-V International announces Andrea Gallo as the organization’s new CEO, effective immediately. Gallo has served as Vice President of Technology at RISC-V International since June 2024. |
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See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit Quadric® today announced that it will showcase its Chimera general-purpose neural processing unit (GPNPU) at the Embedded Vision Summit, May 20-22, 2025, at the Santa Clara Convention Center. |
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Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025 Andes Technology, the leader in RISC-V processor solutions and a Founding Premier member of RISC-V International, will participate as a Gold Sponsor in the prestigious RISC-V Summit Europe 2025 in Paris from May 12-15. Andes will showcase its latest innovations in AI and embedded systems, including a live demo of Android 15 (Vanilla Ice Cream) running on its in-house developed QiLai SoC. |
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Ceva, Inc. Announces First Quarter 2025 Financial Results Total revenue for the first quarter of 2025 was $24.2 million, compared to $22.1 million reported for the first quarter of 2024. Licensing and related revenue for the first quarter of 2025 was $15.0 million, compared to $11.4 million reported for the same quarter a year ago. Royalty revenue for the first quarter of 2025 was $9.2 million, compared to $10.7 million reported for the first quarter of 2024. |
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Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design The new supercomputer integrates Cadence’s industry-leading solvers with NVIDIA HGX B200 systems, NVIDIA RTX PRO 6000 Blackwell Server Edition GPUs and NVIDIA CUDA-X libraries and solver software. |
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RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027 An interesting data point presented by analyst Richard Wawrzyniak of the SHD Group highlighted the growing maturity and penetration of RISC-V technology: an expected flip from license-driven revenue to royalty-driven revenue from RISC-V around 2027, and even sooner if penetration into data centers intensifies (see chart below). |
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Keysom Unveils Keysom Core Explorer V1.0 Keysom, a leader in RISC-V processor Cores and Edge AI solutions, is thrilled to announce the official launch of Keysom Core Explorer V1.0, a groundbreaking platform enabling fast, reliable design exploration and testing of fully customizable RISC-V architectures and their complete software stack. |
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SiFive and Kinara Partner to Offer Bare Metal Access to RISC-V Vector Processors SiFive, Inc., the gold standard for RISC-V computing, today announced that the company has partnered with Kinara to create a USB-based enablement board that provides access to the SiFive IntelligenceTM X280 processor and sample code to allow customers to test out the X280 IP and begin development of RISC-V vector software. T |
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PQSecure Partners with Menta SAS to Demonstrate Leakage-Resistant PQC IPs on eFPGA Fabric PQSecure, a leading provider of high-assurance HW/SW cryptographic IPs, has partnered with Menta to implement and validate its silicon-ready post-quantum cryptographic cores—ML-KEM and ML-DSA—on the Menta M5L40 embedded FPGA (eFPGA). |
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VESA Releases Compliance Test Specification Model for DisplayPort Automotive Extensions Standard Designed to support the latest versions of DisplayPort (version 2.1a) and Embedded DisplayPort (eDP, version 1.5a), VESA’s DP AE standard provides support for end-to-end automotive display functional safety (FuSa) and security. |
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Imagination Announces E-Series: A New Era of On-Device AI and Graphics Imagination Technologies redefines edge AI and graphics system design with the launch of Imagination E-Series GPU IP. E-Series leverages its highly efficient parallel processing architecture to provide exceptional graphics performance while also scaling from 2 to 200 TOPS INT8/FP8 for AI workloads. |
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Kyocera Licenses Quadric's Chimera GPNPU AI Processor IP Quadric® today announced that Kyocera Document Solutions Inc. has licensed the Chimera™ general purpose neural processor (GPNPU) intellectual property (IP) core for use in next generation office automation system on-chip (SoC) designs. |
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MIPI C-PHY v3.0 Adds New Encoding Option to Support Next Generation of Image Sensor Applications Version 3.0 introduces support for an 18-Wirestate mode encoding option, increasing the maximum performance of a C-PHY lane by approximately 30 to 35 percent. This enhancement delivers up to 75 Gbps over a short channel, supporting the rapidly growing demands of ultra-high-resolution, high-fidelity image sensors. |
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Keysight Expands USB Standards Support in System Designer for USB Built as a smart design environment, System Designer for USB enables comprehensive modeling and simulating of systems adhering to the latest USB4® standard. This advanced, system-level approach enables system-level validation, streamlining the path to product release. |
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Cadence Accelerates Physical AI Applications with Tensilica NeuroEdge 130 AI Co-Processor Based on the proven architecture of the highly successful Tensilica Vision DSP family, the NeuroEdge 130 AICP delivers more than 30% area savings and over 20% savings in dynamic power and energy without impacting performance. |
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Axiomise Featured Gold Sponsor at RISC-V Summit Europe Next Week in Paris Axiomise®, the leading provider of cutting-edge formal verification solutions, will feature the effectiveness of its formal verification solutions for corner-case bug hunting at the RISC-V Summit Europe next week in Paris. |
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Agile Analog appoints CEO to drive growth Circuit IP licensor Agile Analog Ltd. (Cambridge, England) has appointed experienced chip executive and entrepreneur Krishna Anne as CEO with a charter to drive growth at the company. |
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Numem Appoints Former Intel Executives to Leadership Team Numem has announced the appointment of two former Intel executives to its leadership team: Rob Crooke and Ashu Bakhle |
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Optimized SAR ADCs, Sigma-Delta ADCs, DACs, and Audio CODECs for IoT, MCU, SoC, and Consumer Applications T2M IP, a global leader in independent semiconductor IP business development, proudly announces the launch of their partner’s latest portfolio of high-performance, low-power Analog and Mixed-Signal IP cores, engineered for next-generation energy-efficient electronic systems. |
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Enabled on makeChip and powered by Racyics, the SpiNNaker2 chip forms the core of the newly launched SpiNNcould supercomputer! SpiNNaker2 was manufactured in 22Fdx technology. It employs Adaptive Body Biasing (ABB) in a Forward Body Bias (FBB) configuration, implemented using Racyics ABX® platform. In combination with Dynamic Voltage and Frequency Scaling (DVFS), this allows for adaptive near-threshold operation down to 0.5V. |
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