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IP / SOC Products Articles

• USB 3.0 - Everything you need to know (Mar. 12, 2015)
  In the last 14 years, the Universal Serial Bus (USB) has become the standard interface to connect devices to a computer. Whether it’s an external hard drive, a camera, the mouse, a printer, or a scanner, the physical connection to transfer data between devices generally is a USB cable. The interface is indeed universal.
  
  
• Security needs more than checklist compliance (Mar. 12, 2015)
  Following a checklist of requirements is only a start for designing security into electronics products.
  
  
• Understand LTE-A Release 12 transmitter architecture: Part 1 (Mar. 11, 2015)
  This two-part article series reviews new developments in the Fourth Generation Long Term Evolution (4G-LTE) cellular standard. The articles explore LTE-Advanced (LTE-A) Release-12 (Rel-12) features and their impact on eNodeB radio frequency (RF) transmitters.
  
  
• Time for multimedia SoCs to get their analog signals right (Mar. 06, 2015)
  Today, cost, power, and area reduction requirements are driving the integration of analog interfaces into multimedia system-on-chips (SoCs). Among other challenges, successful implementation of modern multimedia SoCs requires a good understanding of the most relevant characteristics of analog interfaces and how they can be integrated while ensuring the transmission quality of the analog audio/video signals.
  
  
• Interconnect (NoC) verification in SoC design (Mar. 03, 2015)
  Use a “socket” concept to decouple IP cores from SoC busses.
  
  
• Bluetooth Developer? Why Reinvent the Wireless Radio... Use the CORDIO BT4 Radio IP (Mar. 02, 2015)
  Many developers feel they need to go it alone when inventing a new wireless device, designing every aspect of the device from the ground up. What many forget is that it is often the best approach to buy or license certain parts of the design from other developers who may specialize in just one facet of their overall product. Case in point? Well if you are a Bluetooth developer, and need to have a best-in-class wireless radio, the Sunrise Micro Devices CORDIO BT4 may be just the shortcut to getting to market you are looking for.
  
  
• Dual edge sequential architecture capable of eliminating complete hold requirement from the test path (Mar. 02, 2015)
  Scannability has always been a challenge and with the complex architectures, challenges gets multifold by imposing several limitations like HOLD closure, yield loss, silicon failures due to HOLD, scan architectures and complex scan-shift methodology.
  
  
• The future of custom ASICs (Feb. 26, 2015)
  With the prevailing view that Moore's Law is slowing Donnacha O’Riordan, director of services strategy for S3 Group, gives a view of of accessing IC solutions with IP and tailored silicon solutions.
  
  
• Internet of Things - Opportunities for device differentiation (Feb. 23, 2015)
  The Internet of Things (IoT) is an emerging market trend impacting semiconductor devices, system OEMs, cloud service providers, and internet infrastructure companies. The trade press, accompanied by the types of companies mentioned above, has spilled a lot of ink on the subject, but this is typical in an emerging market with evolving requirements.
  
  
• System Management Controllers (Feb. 17, 2015)
  No other area of modern system design seems as perplexing as the apparently trivial subject of system management controllers—or chassis management, or shelf management, or board management, or any of a half-dozen other terms. The trouble begins with that old demon of design, feature creep.
  
  
• Three types of headset detection to embed in audio converters (Feb. 17, 2015)
  In mobile electronics, a single device suffices to cover various daily usages: calling, taking pictures, playing music, geolocating, etc… All of these common features should fit in one’s hand. To adequately implement these new functionalities, audio electronics must not be limited to basic plug and play functionalities any longer. Smartphone applications should be compliant with new user practices by enabling more interactivity and giving more possibilities to control the inner functionalities.
  
  
• Buffer design for reducing Hold violations & IR drop (Feb. 17, 2015)
  In shrinking technologies, all SoC’s have to work in multi modes and multi corners. So there is a tough challenge to meet setup and hold in all corners. Hold violation closure for a design involves Non-Si Hold closure (due to clock - skew) & Si Hold closure (due to clock and data noise). Non-Si Hold fixing is done by downsizing the existing logic or by putting more hold buffers in the path (primarily of Low drive buffers) while the Si-Hold fixing can be done by adding more buffers.
  
  
• Non-Power-of-Two FFT Circuit Designs Do Not Have to be Difficult (Feb. 09, 2015)
  One reason that the power-of-two FFT dominates the landscape of high performance real-time signal processing applications is the perception that alternative non-power-of-two (NP2) circuits are difficult to implement.
  
  
• Whither Ethernet (Jan. 29, 2015)
  Ethernet is showing up in all sorts of applications for which it is not obviously a good choice. Find out why this keeps happening, and what new areas Ethernet is likely to dominate.
  
  
• USB 3.1 Links Pose Challenges (Jan. 22, 2015)
  The USB 3.1 spec supports data rates up to 10 Gbits/second but poses new hurdles in link-layer design for chip designers, says an expert in the IP group at Synopsys.
  
  
• An MLC ROM With Inserted Redundancy and Novel Sensing Scheme (Jan. 19, 2015)
  An Nor-type MLC ROM, Multi Layer Cell Read Only Memory macro of 16M bits (actual 32M bits) density is presented. The MLC ROM is designed by a 0.090 μm CMOS logic process. The ROM cell of 0.40μm ×0.50μm with 0.03μm per step of the channel width and channel length increase is determined to obtain 4 levels of Ids. A scheme of 2-step sensing with current-to-voltage converter (step1) and an ADC (step2) are applied to obtain an access time of 5 ns. 4 bits per cell can be achieved by inserting more referencing columns of ROM cells to track and to compensate noise from power and ground bouncing.
  
  
• Choosing the Best High-Speed ADC for Your SoC (Jan. 12, 2015)
  Consumer’s voracious appetite for quick access mobile content is obligating the need for high-resolution, high-speed data convertors in their mobile internet devices. Whether the transmission pipe is via cellular networks such as LTE or via local networks such as WiFi, the end requirement for the data convertor remains largely the same, those being higher bandwidth, higher speed, lower power and ownership costs that the consumer market can tolerate. This paper presents the key emerging market requirements for high-speed data-convertors, the metrics to use, and the architectural choices. It completes with a review of a highly efficient SAR ADC.
  
  
• Implement a VXLAN-based network into an SoC (Jan. 09, 2015)
  Here's how to eliminate bottlenecks in hyperscale cloud datacenter SoCs with VXLAN-based networks over 10G Ethernet IP
  
  
• Bridging the gap between speed and power in Asynchronous SRAMs (Jan. 06, 2015)
  The Asynchronous SRAM space is divided between two very distinct product families – fast and low power – each with its own set of features, applications, and price. Fast Asynchronous SRAMs have faster access time, but consume more power. Low-power SRAMs save on power consumption, but have slower access time.
  
  
• A High Density, High Performance, Low Power Level Shifter (Jan. 05, 2015)
  These days, there is a requirement of achieving high frequency targets with lower power consumption. Achieving both the targets simultaneously is very difficult and the situation becomes even more complex while moving down the technology nodes due to various sub-micron effects. With more features being integrated in modern SoC’s, the total number of gates used is increasing. Moreover higher throughput necessitates operating the design at higher frequencies. All this leads to significant increases in power consumption and die size. The proposed circuit is a single supply level shifter to translate the signal from one power domain to another power domain.
  
  
• Sub-Threshold Design - A Revolutionary Approach to Eliminating Power (Dec. 29, 2014)
  Low power IC solutions are in great demand with the rapid advancement of handheld devices, wearables, smart cards and the IoT bringing a massive amount of new products to market that all have the same primary need: Powering the device as long as possible between the need to re-charge the batteries. Ambiq Micro came on the scene four years ago with the goal of creating ultra-low power semiconductor solutions like microcontrollers, real-time clocks, and advanced power management. This white paper shows a 40 year old revived, innovative technique they use in the design of their ICs.
  
  
• Road to Auto Market Paved With Fault-Tolerant SoCs (Dec. 29, 2014)
  Data protection and redundancy features implemented across entire SoC designs will help teams implement functional safety faster and at a higher quality level
  
  
• SoC clock monitoring issues: Scenarios and root cause analysis (Dec. 19, 2014)
  Clocking and Reset circuitry are the backbone of any SOC. With growing complexity of design, scaling of technology and introduction of multi core architecture, there has been an increase in demand of low power support, resulting in multiple clock and power domains. As this increases the level of complexity in the design, there are chances of introduction of clock domain crossing and reset domain crossing related challenges. As a result, greater are the chances of failures/defects, and any defect in this domain can prove catastrophic, especially when dealing with SOCs for the automotive industry.
  
  
• Moore's Law is Dead: Long Live SoC Designers (Dec. 18, 2014)
  Let’s face it, Moore’s Law has been the free lunch program of the semiconductor industry. And now that Moore’s Law is dead, how will SoC designers continue to survive?
  
  
• ESIstream vs. JESD204B for Ultra-High-Speed Chip-Chip Communications (Dec. 18, 2014)
  The open ESIstream protocol has less encoding overhead and higher data bandwidth than JESD204B. It's also significantly easier to implement ESIstream digital core.
  
  
• FPGA-based FSK/PSK modulation (Dec. 15, 2014)
  This article discusses practical application of a combined Binary FSK and PSK modulator. It highlights how embedded resources can be used to implement an all-digital FSK / PSK modulator, which modulates serial data transmission of a UART (Universal Asynchronous Receiver and Transmitter).
  
  
• USB 3.0 vs USB 2.0: A quick reference summary for the busy engineer (Dec. 15, 2014)
  Abhishek Gupta of Cypress Semiconductor shares the quick reference sheet he created to concisely summarize key differences between USB 2.0 and USB 3.0.
  
  
• USB 3.1: Evolution and Revolution (Dec. 15, 2014)
  USB-IF Worldwide Developers Days introduced developers to the new USB 3.1 specification. On the surface, USB 3.1 seems like it could be only an update to 10G speeds, but this white paper will dig deeper into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the USB 3.1 specification. USB 3.1 introduces a new 10 Gbps signaling rate in addition to the 5 Gbps signaling rate defined in the USB 3.0 specification.
  
  
• Driving the Future of Automotive Infotainment with Noise Resilient Audio Converters (Dec. 08, 2014)
  This article describes the main automotive application constraints that have an impact on audio performances and thus consumer experience, together with design considerations to be taken care of at silicon Intellectual Property (IP), Systemon- Chips (SoC), application firmware/software and Printed Circuit Board (PCB) levels.
  
  
• A framework for the straightforward integration of a cryptography coprocessor in SoC-based applications (Dec. 01, 2014)
  In this paper, we describe a versatile IP core providing cryptography and security, complemented with a software wrapper including the necessary low-level drivers and communication interfaces between the Linux OS and OpenSSL, the most-widely used cryptographic library in embedded systems. The