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IP / SOC Products Articles

• H.264/AVC HDTV Motion Compensation Soft IP (Jun. 04, 2009)
  This paper presents a motion compensation soft IP for H.264/AVC decoding based on the MoCHA architecture. The IP was designed in VHDL and validated by simulation and by prototyping on a Xilinx FPGA platform.
  
  
• Low Power High Speed All Digital Phase Locked Loops (Aug. 11, 2008)
  In this paper an All Digital phase locked loop is proposed. This PLL can accomplish faster phase lock. Additionally, the functions of frequency comparator and phase detector have been improved and are well synchronized.
  
  
• AMASS Core: Associative Memory Array for Semantic Search (Aug. 07, 2008)
  This paper presents de specification, design and implementation of a high performance search engine core. This core implements a regular Associative Memory Array processing in HW and non-structured data management in SW.
  
  
• Hardware Security Requirements for Embedded Encryption Key Storage (Aug. 04, 2008)
  As the sophistication of global competitors and IP thieves in countries with weak IP protections increases, there exists an increased need for enhanced physical security for sensitive security information such as encryption keys.
  
  
• Antifuse memory IP fuels low-power designs (Aug. 04, 2008)
  Embedded nonvolatile memory is becoming more prevalent in a wide range of chips, particularly for power-sensitive applications.
  
  
• DesignTag: A Thermally Sensed Security Tag to Protect Chip Designs (Jul. 28, 2008)
  This paper introduces a novel "security tag" technology for detecting misuse of semiconductor intellectual property, in the form of a small circuit which is added to the chip design.
  
  
• Low Power Asynchronous Processor With Cordic Co-Processor (Jul. 21, 2008)
  This paper describes the architectural design of RISC based asynchronous microprocessor as an alternative to clocked design.
  
  
• How to select an AES solution (Jul. 16, 2008)
  To achieve higher data throughput designers can use an ASIC or FPGA platform to provide hardware acceleration.
  
  
• FPGA Implementation of DLX Microprocessor With WISHBONE SoC Bus (Jul. 03, 2008)
  DLX is an open source microprocessor, it’s free and it has never been implemented in a commercial ASIC (Application Specific Integrated Circuit) design. The objective of this project is to use the DLX microprocessor implemented with Wishbone bus interface for a SoC (System-on-Chip) design.
  
  
• Reducing system complexity by using a single-supply logic-level shifter (Jul. 03, 2008)
  This article discusses an innovative, multiple-voltage level-shifter topology which demonstrates the dependence of digital circuits on analog fundamentals such as rise/fall times, capacitance, and current/voltage sourcing/sinking
  
  
• Lower voltage next goal for low-power DDR (Jun. 23, 2008)
  Low-power DDR2 (LPDDR2), a next-generation low-power memory technology for mobile and embedded designs that's being defined by companies participating in Jedec standards, offers higher speed, lower- voltage operation, larger capacities and lower pin count than the current generation--and lets nonvolatile memory share the same bus as SDRAM.
  
  
• Keeping the best audio quality in mobile phone by managing voltage drops created by 217 Hz transients (Jun. 19, 2008)
  Whatever the protocol used by a mobile phone, GSM or TDMA, RF transmitter switching creates the most notorious noise for the power supply.
  
  
• ESD and EMI hazards in mobile phones--Solutions for the audio system connector (Jun. 19, 2008)
  This article briefly discusses the causes and consequences of ESD and EMI hazards in the audio system of mobile phones. The uses of ESD suppressors and EMI filters to avoid these hazards are discussed. Finally, three currently available solutions are compared.
  
  
• Mobile DDR spurs low-cost, low-power automotive electronics designs (Jun. 12, 2008)
  In the memory unfriendly automotive environment, designers are having to seek out more and different system memory solutions. Here's one of the newest.
  
  
• Enhance circuit timing design with programmable clock generators (Part 1 of 2) (Jun. 05, 2008)
  As clocks speed increase and the number of clocks increases, a programmable clock generator may offer a better system and EMI design solution
  
  
• Enhance circuit timing design with programmable clock generators (Part 2 of 2) (Jun. 05, 2008)
  As clocks speed increase and the number of clocks increases, a programmable clock generator may offer a better system and EMI design solution
  
  
• NV memory beyond floating gateNV memory innovators (May. 29, 2008)
  Many applications need to archive data or retain system information after power-down. These tasks fall to nonvolatile memory that must be in-circuit writable at least once, and often many times. Floating-gate data storage, the traditional technology used to create such NV memory, faces increasing challenges as process lithography shrinks, prompting evolving new technologies to take over.
  
  
• Re-Use of Verification Environment for Verification of Memory Controller (May. 27, 2008)
  With the complexity of the design on the rise, coverage of functional verification is one of the increasing challenges faced by the design and the verification teams. Reducing the verification time without compromising the quality of the verification is the greatest challenge to the verification engineers.
  
  
• An MDE Approach For Implementing Partial Dynamic Reconfiguration In FPGAs (May. 22, 2008)
  In this paper, we present a work in progress to provide high level modeling of PDR and a design flow to automatically generate VHDL code from these high level models depending on QoS criteria such as reconfiguration time, performance and power consumption.
  
  
• Multimode: How to design a programmable baseband device for multiple wireless standards (May. 22, 2008)
  A programmable solution integrated into the main application processor will create a new breed of value-added devices far beyond the current view of communication devices.
  
  
• Massively parallel processing arrays (MPPAs) for embedded HD video and imaging (Part 1) (May. 19, 2008)
  This is the first of two articles discussing how Massively Parallel Processing Arrays (MPPAs) can be used to accelerate high-performance embedded system applications. In this article, we discuss the requirements of high-performance applications and how MPPAs compare with other architectures.
  
  
• Configurable SoC Platform for Bluetooth Applications (May. 15, 2008)
  This paper describes the development of a configurable SoC platform using configurable IP cores, which is designed for low cost, low power and targeted for Bluetooth® and ULP (Ultra Low Power) Bluetooth standalone applications.
  
  
• H.264 encoder design using Application Engine Synthesis (May. 12, 2008)
  The goal was to build an H.264 video encoder that would meet real-time requirements of 30 frames per second at D1 resolution with completion in less than 5 months.
  
  
• An Efficient Software-Hardware Partitioning for Transport Demultiplexer (May. 05, 2008)
  In this paper, we present an efficient software-hardware partitioning for transport demultiplexer. We develop transport demultiplexer software model and simulate it on reduced instruction set computer (RISC).
  
  
• IP Core of On-line ICA Algorithm (May. 01, 2008)
  We propose IP core of on-line ICA algorithm. The on-line ICA algorithm can decompose input signals into statistically independent components. We demonstrate that we can recover original chaotic signals from linearly mixed chaotic signals without any information of mixing.
  
  
• System Packet Interface (SPI) 4.2 IP Core (Apr. 28, 2008)
  The paper describes the architecture of a novel performance-enhanced SPI 4.2 IP Core. It also mentions, through examples and performance statistics, the improvement in the performance of SPI 4.2 data transfer as against the sub-optimal IP cores available.
  
  
• Serial ATA and the evolution in data storage technology (Apr. 28, 2008)
  No question, storage devices and storage technologies have helped fuel our digital lifestyle. The amount of storable information and the requirement for fast, efficient, state-of-the-art storage technologies are the primary mechanisms that must continue to evolve if we are to meet the demands for all things digital.
  
  
• Overcome power, size and cost when developing optimized '4G' chipsets for handhelds (Apr. 24, 2008)
  Here is an overview of three dimensions that should be addressed by 4G chip developers to minimize the power consumption, size and cost of their solutions.
  
  
• FPGA-based flexible Ethernet switch reduces development time (Apr. 21, 2008)
  The real time capability of networks that use the IEEE 1588 Precision Time Protocol is limited. This novel FPGA based switch eliminates the problem by implementing 1588 boundary/transparent clocks and gives developers the opportunity to leverage the flexibility of the FPGA to easily support multiple standards, quickly support standard changes and easily add custom features to the switch.
  
  
• C-based coprocessor design, part 1: SIMD architecture (Apr. 17, 2008)
  Here's how CebaTech's C2R C-to-RTL compiler was used to implement a G723.1 and G729.A speech coding accelerator. The accelerator, which attaches to a scalar processor core, features configurable micro-architecture and instruction-set architecture.