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IP / SOC Products Articles

• Fully Digital Implemented Delta-Sigma Analog to Digital Converter (Dec. 18, 2006)
  This paper shows an approach which only uses 2 resistors and 1 capacitor which are located outside a pure digital chip. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the ADC also can be used for FPGAs.
  
  
• SPI-S--a next-generation interface for serial physical interconnects (Dec. 18, 2006)
  SPI-S delivers a channelized, streaming-packet interface scaleable to hundreds of Gb/s for chip-to-chip and backplane applications using OIF CEI interconnects with either 64B66B or CEI-P framing. By leveraging existing FPGA and ASIC SERDES technology SPI-S will not require new development for its physical interface.
  
  
• PoP, SiP, MCM, MCP or SoC? Assessing the mobile/embedded design tradeoffs (Dec. 15, 2006)
  Multichip packages (MCPs) have long met the need to pack more performance and features into an increasingly small space. It seems natural to see the extension of the memory MCP to include ASICs such as basebands or multimedia processors. But here, we run into the difficulties of development and ownership/reduction costs.
  
  
• A Platform-Based Technology for Fault-Robust SoC Design (Dec. 11, 2006)
  When designing a System-On-Chip (SoC) for safetycritical or high-reliability applications, the design space that a system architect must consider is rather large due to the variety of faults that can affect the SoC, the different failures that these faults can generate and the wide set of techniques that can be used to detect, confine or stop the resulting hazards, each one with its efficiency and cost.
  
  
• Codec from Canada, CRC-WVC, outperforms H.264 video with wavelets (Dec. 07, 2006)
  The structure and algorithms of a new wavelet-based video codec called CRC-WVC with compression efficiency that can perform better than H.264/MPEG-4, and with room for further improvements
  
  
• System on Chip (SoC) for Short Range Wireless - CMOS versus SIGe (Nov. 27, 2006)
  Wireless communication is becoming more and more commoditized. While newer technologies such as UWB and 802.11n are still in the early adopter phase, with time to market being the primary driver, the markets for Bluetooth and 802.11abg are maturing, meaning that cost reduction becomes the primary goal
  
  
• Media SoC design for reduced power consumption (Nov. 24, 2006)
  Architectures that are ''power conscious'' use design techniques to reduce the overall gate count and power consumption while efficiently handling data transactions.
  
  
• Achieving multicore performance in a single core SoC using a multi-threaded virtual multiprocessor: Part 1 (Nov. 20, 2006)
  Designers everywhere face ever increasing constraints on system cost and power consumption, while at the same time being required to add more performance and functionality to their designs. This is a difficult trade-off to address successfully.
  
  
• Tutorial: Improving the transient immunity of your microcontroller-based embedded design - Part 2 (Nov. 17, 2006)
  The hardware design techniques employed for an application will establish the baseline immunity performance. The purpose of hardware techniques is to reduce the level or frequency content of immunity signals below that needed to cause performance degradation or long-term microcontroller (MCU) reliability problems.
  
  
• Integrating 'hard' IP into a system-on-chip (Nov. 16, 2006)
  The integration of ''hard'' intellectual property blocks--those delivered as GDSII databases--lets system designers focus on their core competency by outsourcing certain blocks that previously had to be developed internally.
  
  
• Diamond Standard Processor Core Family Architecture (Nov. 06, 2006)
  This white paper explores the design of the Xtensa base instruction set architecture (ISA) and illustrates the impact of architecture on performance. It traces the evolution of modern instruction-set design and compares key features of Tensilica’s architecture with previous instruction set architectures. It provides a detailed rationale for the major architectural innovations in the Xtensa ISA.
  
  
• Video processing approaches for a portable multimedia SoC (Oct. 30, 2006)
  Comparing the three main approaches for developing multimedia based SoCs -- hardwired accelerators, video co-processors and general purpose processors.
  
  
• How to design FPGA-based advanced PCI Express endpoint solutions (Oct. 19, 2006)
  Currently dominating the desktop PC motherboard and graphics markets, the PCI Express protocol is poised to supplant PCI and PCI-X interface as the dominant high-bandwidth interconnect for the server, enterprise, mobile, workstation, networking, communica
  
  
• Hit performance goals with configurable processors (Oct. 19, 2006)
  With mainstream DSPs, code must be hand-tuned using assembly code in order to meet performance goals. A more productive approach is to tailor the processor to the algorithm. This article explains why, using FFT, Viterbi, and MPEG4 examples.
  
  
• Smart partitioning in WiMAX radios illustrates design challenges, Part 1 (Oct. 13, 2006)
  Deciding how to split mixed-signal functions between two or more die is a complex exercise in balancing design tradeoffs, as this WiMax design shows
  
  
• JPEG2000 codec for robust, scalable pro and consumer video (Oct. 13, 2006)
  The JPEG2000 wavelet-based algorithm generates a compressed codestream that retains the ability to easily extract different representations of the image, including different frame dimensions, without transcoding or recompressing
  
  
• Implementing matrix inversions in fixed-point hardware (Oct. 12, 2006)
  We implement fixed-point matrix inversion on a Virtex-4 FPGA using a synthesizable QR-decomposition MATLAB model and the AccelDSP Synthesis tool. The resulting function occupies 12% of a XC4VSX55 device and has a 1.7 MSPS data rate.
  
  
• How to cascade external storage with Serial ATA (Oct. 09, 2006)
  Serial Advanced Technology Attachment (SATA) has become the dominant interface for internal storage in desktops, notebooks and consumer electronics devices.
  
  
• How to increase confidence that third-party IP is functionally correct (Oct. 09, 2006)
  The EDA industry has provided designers with a vast arsenal of tools that can be used to verify the functional correctness of an IP design
  
  
• System Solutions for a Baseband SoC (Oct. 02, 2006)
  This article considers the ARM solutions that address these issues. To give a real-world focus, we present the TTPCom’s CBEmacro 3G modem as an example
  
  
• High-definition video scaler ASIC development from FPGA (Oct. 02, 2006)
  This article details the implementation and verification flows of a high-definition video scaler ASIC implemented in a 0.18um standard cell technology
  
  
• Meeting the High-Speed Serial Link Challenge (Sep. 28, 2006)
  The electronics industry is in the midst of a dramatic shift away from traditional parallel communication standards and towards new, high-speed serial interface technologies. This article details the standards supporting this change, challenges designers
  
  
• How to simplify switch-mode DC-DC converter design (Sep. 27, 2006)
  This article focuses on the design issues that are simplified by including an integrated inductor optimized for a range of electrical and layout applications as part of the power management solution
  
  
• Creating multi-standard, multi-resolution video engines using configurable processors (Sep. 18, 2006)
  Customize the processor to your video application by creating instructions, register files, functional units and interfaces that accelerate the processing
  
  
• Why outsource the interconnect? (Sep. 18, 2006)
  The widespread use of wireless communications and the rise in digital content consumption in handsets are creating new opportunities and correspondingly new system design challenges for OEMs
  
  
• Designing for Security - Why Software Isn't Enough (Sep. 07, 2006)
  This article exposes some of the issues that are often overlooked when designing today’s security architectures and provides a discussion of high-integrity security solutions that create a hardware-enforced security environment.
  
  
• How to get the best cost savings when implementing an FPGA-to-ASIC conversion (Sep. 07, 2006)
  Planning an FPGA-to-ASIC conversion requires that the ASIC vendor is involved as early as possible in order to achieve the best cost savings
  
  
• ESD protection for HDMI 1.3 interfaces (Sep. 07, 2006)
  The hot-plugging capability of HDMI ports makes ESD protection a must.
  
  
• Beyond DDR2 400: Physical Implementation Challenges in Your SoC Design (Sep. 05, 2006)
  Using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks associated with combining discrete memory subsystem blocks, such as interoperability and schedule. Packaged as a complete, integrated place-and
  
  
• H.264 decoder test takes careful planning (Sep. 01, 2006)
  The testing of advanced video decoders is a daunting task, considering the greater complexity and nonlinearity of H.264 compared with MPEG-2. Decoding depends on numerous contexts and states that one would be very unlikely to encounter through random inte