D&R Industry Articles | Most Popular | SoC News Alerts |

IP / SOC Products Articles

• RF ICs can be quite complex (Sep. 06, 2005)
  by Cedric Paillard, Semiconductor Insights
  
  
• Balancing power and experience (Sep. 01, 2005)
  by Kevin McIntyre, IEM Product Manager, ARM Holdings
  
  
• How to Protect Intellectual Property in FPGA Devices--Part2 (Aug. 30, 2005)
  IP theft is becoming a major problem. Estimates are that 186 counterfeit ICs are available. Protect your FPGA IP
  
  
• Easing verification challenges for IP reuse (Aug. 22, 2005)
  by Brian Bailey
  
  
• Advanced modeling verifies backplane designs (Aug. 15, 2005)
  First it was single ended drivers, then differential pairs, and now adaptive drivers and receivers are used to coax data down copper interconnects as fast as possible
  
  
• Enabling Video for Handset and Handheld Devices (Aug. 10, 2005)
  Falanx Microsystems Whitepaper
  
  
• A Design of System on a Chip for Voice over Wireless LAN (Aug. 04, 2005)
  VoIP SoC(System on a Chip) over wireless LAN is presented, which integrates u-processor, wireless access block, several user interfaces and voice signal interfaces
  
  
• Selecting PCI Express IP for Your Design (Jul. 28, 2005)
  This application note provides you with a very brief introduction to the emerging PCI Express protocol and explains how selecting the right digital and mixed signal IP can accelerate the implemention of this new standard into your designs.
  
  
• Replacing flash memory for embedded applications (Jul. 27, 2005)
  XPM is an alternative to flash memory from new company Kilopass
  
  
• Integrating Linear Power Regulation On-Chip (Jul. 21, 2005)
  Power regulation and management IC’s have become one of the fastest growing segments of the electronics industry largely due to the proliferation of portable electronic devices such as cell-phones, MP3 players, PDA’s, and game machines
  
  
• Getting the most from multiprocessor SoC design (Jul. 20, 2005)
  For many applications, allocating performance among all of the tasks in a system-on-chip (SoC) design is much easier and provides greater design flexibility with multiple CPUs than with just one control processor and multiple blocks of logic
  
  
• A Real-Time Image Processing with a Compact FPGA-Based Architecture (Jul. 19, 2005)
  In this paper we present a filed programmable gate array implementation of a real time video smoothing algorithm.
  
  
• NOR continues to battle NAND flash memory in the handset (Jul. 12, 2005)
  With NOR- and NAND-type flash memory jockeying for position, there's considerable debate over whether these technologies will coexist or compete. Semiconductor Insights' recent teardown of the NEC FOMA 900iL handset brings this question to bear.
  
  
• Simultaneous Exploration of Power, Physical Design and Architectural Performance Dimensions of the SoC Design Space using SEAS (Jul. 11, 2005)
  In this paper we discuss extensions to SEAS in the areas of physically-aware power optimization through voltage island physical planning, transaction level functional simulation platform for embedded software development, and a transaction level power ana
  
  
• Using a "DSP-free" design for VOIP-enabled end-points (Jul. 11, 2005)
  While ever-increasing volume demands help to drive some economies of scale, OEMs and ODMs are also looking to minimize product costs without sacrificing features or call quality.
  
  
• AICP: AURA Intelligent Co-processor for Binary Neural Networks (Jul. 07, 2005)
  AURA (Advanced Uncertain Reasoning Architecture) is a generic family of techniques and implementations intended for high-speed approximate search and match operations on large unstructured datasets
  
  
• Micro-threaded Row and Column Operations in a DRAM Core (Jul. 04, 2005)
  The technique of micro-threading may be applied to the core of a DRAM to reduce the row and column access granularity. This results in a significant performance benefit for those applications that deal with small data object
  
  
• Digital Associative Memories Based on Hamming Distance and Scalable Multi-Chip Architecture (Jun. 30, 2005)
  In this paper, we present a new concept and its circuit implementation for high-speed associative memories based on Hamming distance
  
  
• Adapting partially programmable ASSPs to vehicle design needs (Jun. 24, 2005)
  By providing an element of part programmability—a portion of the chip design that can be tailored to the specific needs of the application—engineers can obtain an ASIC or ASSP that exactly meets their needs.
  
  
• Accelerating Nios II Ethernet Applications (Jun. 23, 2005)
  This paper describes methods for accelerating Nios® II embedded processor TCP/IP Ethernet applications.
  
  
• Application Specific Real-Time Microkernel in Hardware (Jun. 23, 2005)
  This article demonstrates that a hardware based real-time kernel can keep or increase the performance of a monolithic structured real-time operating system, while improving system modularity.
  
  
• IP Processor Core Platform Selection According to SoC Architecture: a case study (Jun. 22, 2005)
  This work aims to compare several IP core processor based platforms according to the following key parameters: FPGA architecture, coprocessor and accelerator integration, RTOS and HW-SW refinement tools
  
  
• Managing multiple evaluations of analog IP (Jun. 20, 2005)
  An analog and mixed-signal IP company needs to excel using its creative resources, so it must leverage core skills to produce a growing product portfolio. But with customer evaluations becoming increasingly complex, it is just as necessary to leverage sca
  
  
• Embedding FPGAs in DSP-driven Software Defined Radio applications (Jun. 13, 2005)
  With the advent of software defined radio platforms in military aerospace and now more recently in some consumer radio and electronics segments, the usefulness of Field programmable logic (FPGAs) as reprogrammable digital signal processing (DSP) SDR engi
  
  
• Fit multimedia handsets with the right memory architecture (Jun. 09, 2005)
  3G is here, and it's one of the most talked-about, high-profile topics in the mobile and wireless industry
  
  
• Implementing Power Management IP for Dynamic and Static Power Reduction in Configurable Microprocessors using the Galaxy Design Platform at 130nm (Jun. 08, 2005)
  by Dan Hillman, Virtual Silicon and John Wei, Tensilica
  
  
• Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects (Jun. 02, 2005)
  by Jerry C. Chen -- Genesys Logic America, Inc.
  
  
• The Challenge of Keeping IP Usable (Jun. 02, 2005)
  by Phil Rose, Cadence Design Systems
  
  
• Platform to Validate SoC Designs and Methodologies Targeting Nanometer CMOS Technologies (May. 26, 2005)
  by Samuel Picchiottino, Mario Diaz–Nava*, Benoit Foret, Sylvain Engels, Robin Wilson from STMicroelectronics, Crolles, France -- *STMicroelectronics, Grenoble, France
  
  
• Interconnects-Keys to the New Car Sensors (May. 23, 2005)
  By Scott Monroe, system architect for mixed-signal automotive at Texas Instruments Inc. (Dallas)