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IP / SOC Products Articles

• Building security into an AI SoC using CPU features with extensions (Apr. 12, 2021)
  With the rapid deployment of artificial intelligence (AI), the focus of AI system on chip (SoC) design has been on building smarter, faster and cheaper
  
  
• CAVP - NIST ACVTS - Are you still with me? (Apr. 01, 2021)
  How “Acronym Soup” Serves Up Big Security Advantages.
  
  
• Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications - PART 3 : Optimizing latency key factor (Mar. 29, 2021)
  In this third part of Paving the way for the next generation audio codec for the True Wireless Stereo (TWS) applications whitepaper, the latency performance and how it impacts the ANC performance will be detailed.
  
  
• Basics of SRAM PUF and how to deploy it for IoT security (Mar. 25, 2021)
  This article covers the basics of what an SRAM PUF (physical unclonable function) is and how it works, as well as the functionality it offers in internet of things (IoT) security as the trust anchor for any device.
  
  
• Colibri, the codec for perfect quality and fast distribution of professional AV over IP (Mar. 18, 2021)
  When you look to transition your AV distribution from dedicated cabling to IP networks, one of the considerations is quality. How much of the quality of your rich visual communication has to be sacrificed in order to run it over 1Gbit Ethernet cables?
  
  
• Increasing bandwidth to 128 GB/s with a tailored PCIe 6.0 IP Controller (Mar. 16, 2021)
  While the PCIe 6.0 specification is expected to be finalized and released later in 2021, PLDA has been hard at work to address the needs of early adopters looking for the most advanced PCIe 6.0 IP solution for their SoCs and ASICs.
  
  
• A RISC-V ISA Extension For Ultra-Low Power IoT Wireless Signal Processing (Mar. 15, 2021)
  This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers.
  
  
• Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications - PART 2 : Increasing play time (Mar. 15, 2021)
  In this second part of Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications whitepaper, energy efficiency will be discussed and several means to achieve extra-long playtime will be exposed.
  
  
• How MIPI Alliance specs enable the IIoT (Mar. 08, 2021)
  This article explains how MIPI specifications, which are widely implemented within billions of mobile devices, can be leveraged by developers to create successful device designs, drive down development efforts and reduce costs across a number of IIoT applications.
  
  
• Standardized PUF-based Solution for Device eID (Mar. 08, 2021)
  In this column, after a background introduction, we will first discuss IEEE 802.1AR standard on secure device identity. Next, we’ll assert PUF is an enabling solution for the device eID. Third, we will discuss PUF related international standards. Fourth, we will present a short tutorial on PUFiot. Fifth, we will assert that PUFiot is an ideal Device eID with wide applications. Finally, we will draw a conclusion on the future trend of Device eID development.
  
  
• Paving the way for the next generation audio codec for the True Wireless Stereo (TWS) applications - PART 1 : TWS challenges explained (Mar. 01, 2021)
  The audio market for wireless Bluetooth headsets is growing rapidly. Audio devices using Bluetooth (BT) connectivity are more ubiquitous than ever. People have gotten used to wireless audio systems, and the mobile phone industry is pushing towards a world without audio connectors and cables. The latest trend in wireless headsets and speakers is True Wireless Stereo systems (TWS), consisting of two independent units that are each charged in their own charging case.
  
  
• Licensing Interconnect IP for Fun & Profit (Feb. 25, 2021)
  “Build or buy” is an age-old question. But here’s another one: Why do you even license IP? Nobody builds their own Mercedes-Benz from scratch. Even if you’re a third-generation, dyed-in-the-wool automotive engineer from Stuttgart, you still won’t build your car. You buy it.
  
  
• Specifying a PLL Part 3: Jitter Budgeting for Synthesis (Feb. 22, 2021)
  This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.
  
  
• Consider ASICs for implementing functional safety in battery-powered home appliances (Feb. 18, 2021)
  This article looks at how functional safety can be applied in home appliances, and examines the economic tipping point of taking an ASIC vs. discrete component route to do so.
  
  
• Enabling AI Vision at the Edge (Feb. 17, 2021)
  Computer vision has made tremendous advances in the last several years due to the proliferation of AI technology. The intersection of big data and massive parallel computing changed the way in which machines are programmed to understand unstructured 2D and 3D data, such as video feeds from cameras.
  
  
• Retiming USB4 over USB-C (Feb. 12, 2021)
  The USB-C connector is the one connector to rule them all. It has wonderful flexibility in its definition and has been widely adopted across different
  
  
• I-fuse: Most Reliable and Fully Testable OTP (Feb. 08, 2021)
  Patented by Attopsemi™, I-fuse™ is a revolutionary non-breaking fuse technology that can be reliably programmed by heat assisted electromigration below a break point. Any cell can be tested as programmable if the initial fuse resistance is low enough (e.g. <400 ohms) to generate enough heat for programming.
  
  
• PUF is a Hardware Solution for the Sunburst Hack (Jan. 26, 2021)
  On December 14, 2020, SolarWinds, which provides network monitoring software to the US government and private businesses, reported one of the largest cyberattacks in history, breaching the data of as many as 18,000 organizations and companies.
  
  
• USB 3.2: A USB Type-C Challenge for SoC Designers (Jan. 26, 2021)
  This white paper outlines applications that benefit from USB 3.2’s increased bandwidth, describes the USB 3.2 specification for USB Type-C™, and explains how the specification affects speed using USB Type-C connectors and cables.
  
  
• It's Time to Look at FD-SOI (Again) (Jan. 25, 2021)
  The emergence of FD-SOI, (fully depleted silicon-on-insulator) and its subsequent maturity over the years, has made it one of the seminal process advancements for low power semiconductor design. Although not as prevalent as the mainstream bulk CMOS process, FD-SOI has provided an important set of benefits to semiconductor product designers.
  
  
• Verifying Dynamic Clock switching in Power-Critical SoCs (Jan. 18, 2021)
  As technology advance, we see complex SoCs emerging in the market with multiple interfaces. These complex SoCs can have multiple clocks driving multiple modules, which may be getting divided further to generate new clocks in the chip and so the complexity increases.
  
  
• Let's make RISC-V connected systems synonymous with security (Jan. 14, 2021)
  If you are designing systems based on a RISC-V architecture, for example to run highly connected applications, you want to include tight, future-proof security. Both for your customers’ experience and your reputation, you want to avoid a breach of security – leaking private data or even changing the functionality. Therefore, security should be part of the fabric of your system.
  
  
• Quantum Tunneling Mechanism in NeoFuse (Jan. 13, 2021)
  NeoFuse is a logic-process compatible non-volatile memory (logic-NVM) using impedance change for data storage in one-time programming (OTP) applications.
  
  
• IO and multiprotocol processing in highly demanding embedded architectures (Jan. 11, 2021)
  Low physical I/O protocols or device management have always been handled by a hardware device, simply because line survey or reaction to a bus change need very short reaction time. It would require a huge amount of processing power in order to be fast enough to comply with the bus management physical and timing requirements.
  
  
• The Four Angles of Examining PUF (Jan. 04, 2021)
  The security of AIoT devices has become increasingly important. In order to ensure that the system’s security functions are working effectively and protecting every node and edge device from information security risks, it is important to generate a unique root of trust in the security system rooted in the chip.
  
  
• The Growing Market for Specialized Artificial Intelligence IP in SoCs (Nov. 26, 2020)
  Over the past decade, designers have developed silicon technologies that run advanced deep learning mathematics fast enough to explore and implement artificial intelligence (AI) applications such as object identification, voice and facial recognition, and more.
  
  
• The Future Of Chip Design (Nov. 23, 2020)
  The future of chip design in a few short years could look entirely different as the semiconductor industry witnesses an advancing trend toward free and flexible, community-supported hardware designs for the long tail of new applications based on custom semiconductor devices
  
  
• Seize the Ethernet TSN Opportunity (Nov. 16, 2020)
  The following sections will take a look at the major Ethernet performance issues and how the extensions address those shortcomings. This will be followed by an overview of the applications of TSN for 5G, industrial automation, automotive invehicle communications and avionics. The paper will conclude with a description of Ethernet TSN solutions offered by Comcores.
  
  
• A MAC-less Neural Inference Processor Supporting Compressed, Variable Precision Weights (Nov. 12, 2020)
  This paper introduces two architectures for the inference of convolutional neural networks (CNNs). Both architectures exploit weight sparsity and compression to reduce computational complexity and bandwidth.
  
  
• Optimizing Floorplan for STA and Timing improvement in VLSI Design Flow (Nov. 09, 2020)
  Static timing analysis is a technique of computing of cell delay and interconnect delay in design (known as path delay) and comparing it against constrain (timing specific) set in SDC file. This paper describes the static timing analysis for a specific design mainly about mem2reg reg2mem and reg2reg setup analysis a kind of detecting and solving the setup violation in design.