English
FPGA Design Needs More Than a Face Lift
By Simon Bloch, Mentor Graphics -- Electronic News, 4/27/2005
FPGA design success is based on the promise of getting to hardware fast, while performing system debug on actual hardware. Constant re-spins, including architectural/design changes, are performed until the FPGA meets system requirements. This method works for smaller devices, but obviously fails for high-end FPGAs because the resulting unpredictable design schedules imply unacceptable product slippages and unrealized business.
Related News
- Gidel Launches Lossless Compression IP that Reduces Storage Needs by Over 50%, Utilizing Only 1% of the FPGA, with Low Power Consumption
- Intel FPGA Technology Supports NEC in Face Recognition Technology
- STMicro face-recognition processor includes FPGA core
- Altera Starts Production Shipments of Industry's Highest Memory Bandwidth FPGA
- PolarFire® SoC FPGAs Achieve AEC-Q100 Qualification
Breaking News
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- Keysom Unveils Keysom Core Explorer V1.0
Most Popular
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- Ceva, Inc. Announces First Quarter 2025 Financial Results
- Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
|
E-mail This Article | 
|
|
Printer-Friendly Page |