German company to introduce PLL IP core at DAC


EE Times: German company to introduce PLL IP core at DAC
(06/10/2005 12:52 PM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=164302158

SAN FRANCISCO — Cologne Chip AG plans to introduce a new intellectual property (IP) core design Monday (June 13) at the Design Automation Conference (DAC) in Anaheim, Calif. The core design, C3-PLL-2, is a phase-locked loop (PLL) for frequency synthesizer applications, based on Cologne Chip's Digicc technology design approach. According to Cologne Chip (Cologne, Germany), the core is fully digital, designed for use with standard cell libraries for digital logic, independent of process technology and chip geometry and occupies a smaller silicon space than that of competing technologies. Cologne Chip said information about C3-PLL-2 pricing and availability could be obtained through the company's Web site.
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