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Digital Core Design (DCD) Announces New Improved DF68XX DoCD Debug System
November 8, 2005 – the Intellectual Property (IP) provider - Digital Core Design (DCD) today has announced the release of the new improved 68xx DoCDTM Debug System designed to DF6805/6808/6811 IP Cores.
The DCD’s DoCDTM Debug System provides real-time and non-intrusive debug capability allowing a pre-silicon validation and post-silicon on chip software debugging. DoCDTM is dedicated for all DCD's DF6811, DF6805 and DF6808 core families. It allows a hardware breakpoints, trace, source debugging. The DoCDTM Debug Software can work as a hardware debugger as well as a software simulator. So some tasks can be validated at software simulation level, and after this step the user can continue real-time debugging by uploading a code into silicon.
System-on-Chip designs plagues keen problem with inaccessibility to important control and bus signals, because they lay often behind the physical pins of the device. It makes traditional measurement instrumentation useless. The best way to get around those limitations, for the verification tasks and software debug, is using on-chip debugging tools. Other advantage of on-chip debugger is an improvement of a design productivity in integrated environment with graphical user interface. The ability to display/modify memories content, processor and peripherals register windows along with trace information and ability to see the related C/ASM source code, are the key factors for the facilitation of a design process and a huge step in the productivity increase.
Developing 68xx DoCDTM Debug System, Digital Core Design improved the Debug Software with Source Level Debugging, which consists of the following function: C code execution, line by line, over, out, skip line. Another facility is witch Symbol Explorer provides hierarchical tree view of all the symbols. Thanks to these improvements debugging process became simple, fast and easy.
The Customer can select VHDL/Verilog source code or FPGA Netlists. IP Core is licensed under Single Design or Unlimited Designs options. If you have any questions, please feel free to contact DCD http://www.dcd.pl/acontact.php
For more information about this product please click the link below:
http://www.dcd.com.pl/ashow.php?page=hcdocd
About Digital Core Design
DCD is a private Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house, an expert in IP cores architecture improvements. DCD sells its products and services directly and through its global distribution network. DCD offers VHDL and Verilog high performance and synthesizable IP cores for a speed optimized 8-, 16- and 32-bit processors, peripherals, serial interfaces, floating point arithmetic units and floating point coprocessors. The functionality of IP solutions offered by DCD were up to date appreciated by over 200 licenses sold for over 150 customers worldwide, such as: INTEL, SIEMENS, PHILIPS, TOYOTA, MAXIM, RAYTHEON, OSRAM, GENERAL ELECTRIC, FARADAY, SAGEM and GOODRICH. DCD also became a member of first-class branch partner programs like: AMPP program of ALTERA, AllianceCORE of XILINX, ispLeverCore of LATTICE and IP Catalyst of SYNOPSYS. For more information, please visit: http://www.dcd.pl
The DCD’s DoCDTM Debug System provides real-time and non-intrusive debug capability allowing a pre-silicon validation and post-silicon on chip software debugging. DoCDTM is dedicated for all DCD's DF6811, DF6805 and DF6808 core families. It allows a hardware breakpoints, trace, source debugging. The DoCDTM Debug Software can work as a hardware debugger as well as a software simulator. So some tasks can be validated at software simulation level, and after this step the user can continue real-time debugging by uploading a code into silicon.
System-on-Chip designs plagues keen problem with inaccessibility to important control and bus signals, because they lay often behind the physical pins of the device. It makes traditional measurement instrumentation useless. The best way to get around those limitations, for the verification tasks and software debug, is using on-chip debugging tools. Other advantage of on-chip debugger is an improvement of a design productivity in integrated environment with graphical user interface. The ability to display/modify memories content, processor and peripherals register windows along with trace information and ability to see the related C/ASM source code, are the key factors for the facilitation of a design process and a huge step in the productivity increase.
Developing 68xx DoCDTM Debug System, Digital Core Design improved the Debug Software with Source Level Debugging, which consists of the following function: C code execution, line by line, over, out, skip line. Another facility is witch Symbol Explorer provides hierarchical tree view of all the symbols. Thanks to these improvements debugging process became simple, fast and easy.
The Customer can select VHDL/Verilog source code or FPGA Netlists. IP Core is licensed under Single Design or Unlimited Designs options. If you have any questions, please feel free to contact DCD http://www.dcd.pl/acontact.php
For more information about this product please click the link below:
http://www.dcd.com.pl/ashow.php?page=hcdocd
About Digital Core Design
DCD is a private Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house, an expert in IP cores architecture improvements. DCD sells its products and services directly and through its global distribution network. DCD offers VHDL and Verilog high performance and synthesizable IP cores for a speed optimized 8-, 16- and 32-bit processors, peripherals, serial interfaces, floating point arithmetic units and floating point coprocessors. The functionality of IP solutions offered by DCD were up to date appreciated by over 200 licenses sold for over 150 customers worldwide, such as: INTEL, SIEMENS, PHILIPS, TOYOTA, MAXIM, RAYTHEON, OSRAM, GENERAL ELECTRIC, FARADAY, SAGEM and GOODRICH. DCD also became a member of first-class branch partner programs like: AMPP program of ALTERA, AllianceCORE of XILINX, ispLeverCore of LATTICE and IP Catalyst of SYNOPSYS. For more information, please visit: http://www.dcd.pl
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