English
Leading Acceleration Technology Company Selects Denali for Memory System Design
Databahn Memory Controller IP Helps ClearSpeed Achieve High-Speed Data Transfers
PALO ALTO, Calif., February 15, 2006 -- Denali Software today announced that its Databahn™ memory controller intellectual property (IP) has been licensed by ClearSpeed Technology (LSE: CSD) for use in acceleration technology designs. ClearSpeed engineers implemented Databahn memory controller IP in the CSX600 coprocessor where it was configured to control the chip's interface to 64-bit DDR2 DRAM with ECC.
"We are pleased to have chosen Denali's Databahn memory controller IP to help us achieve the high quality DDR memory system design," says Russell David, vice president of engineering at Clearspeed. "There was a clean path for configuring the Databahn IP to deliver optimal performance for the CSX600, and we ended up with a very high-quality memory sub-system. We plan to use Databahn again in our next-generation product."
ClearSpeed Technology is a semiconductor company focused on delivering high-performance coprocessors and boards to be used alongside general-purpose processors in the world's most compute-intensive applications. ClearSpeed recently demonstrated the Advance™ board, (which contains two CSX600s) on a standard system which increased the performance by 4x to 30.2 Gigaflops sustained LINPACK while reducing the overall power by about 10 percent compared to running the system on its own. The Advance board is targeted at data-intensive applications in such areas as financial, life sciences, computational chemistry, biology and computer-aided design for fluid dynamics.
"ClearSpeed is delivering some very impressive products in terms of enabling high-performance processing while solving the heat and power problem," remarks Brian Gardner, vice president of IP products at Denali, who adds that ClearSpeed's technology is amazing. "While our Databahn IP has been used successfully in wide range of applications, from handsets to enterprise servers, this is clearly one of the more interesting applications. Delivering this kind of performance is a testament to the quality and configurability of our IP products. We are proud to have ClearSpeed as a customer."
About Databahn
Licensed for use in more than 170 designs, and with more than 65 chips in production, Databahn is the industry-leading memory controller IP solution. Databahn cores offer configurability to deliver optimal performance for a wide range of end applications, and are silicon proven in more than 18 process nodes. To ensure compatibility with all the latest high-speed memory technologies, the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, GDDR3, and Mobile DDR-SDRAM devices from all major memory vendors. Deliverables include: register transfer level (RTL) and synthesis scripts, silicon-independent DDR PHY, verification testbench, static timing analysis (STA) scripts, programmable register settings and documentation. Databahn IP is library independent and covers solutions from .18-micron to .09-micron technologies, and DRAM device frequencies from 100-400MHz (200-800MHz data rate).
About Denali
Denali Software Inc. is the world's leading provider of Electronic Design Automation (EDA) and Intellectual Property (IP) products for design and verification of semiconductor chip interfaces. Denali's Databahn™ and Dataplex™ IP products provide control and optimal data throughput for external DRAM and Flash memory devices. The PureSpec™ and MMAV™ verification IP products support all standard interfaces, including DRAM, Flash, PCI Express, ASI, AMBA, USB, Ethernet, Serial ATA, and CE-ATA. Denali's Blueprint product provides complete solution for on-chip register design and management. For more information, visit Denali at http://www.denali.com, call (650) 461-7200 or email info@denali.com.
PALO ALTO, Calif., February 15, 2006 -- Denali Software today announced that its Databahn™ memory controller intellectual property (IP) has been licensed by ClearSpeed Technology (LSE: CSD) for use in acceleration technology designs. ClearSpeed engineers implemented Databahn memory controller IP in the CSX600 coprocessor where it was configured to control the chip's interface to 64-bit DDR2 DRAM with ECC.
"We are pleased to have chosen Denali's Databahn memory controller IP to help us achieve the high quality DDR memory system design," says Russell David, vice president of engineering at Clearspeed. "There was a clean path for configuring the Databahn IP to deliver optimal performance for the CSX600, and we ended up with a very high-quality memory sub-system. We plan to use Databahn again in our next-generation product."
ClearSpeed Technology is a semiconductor company focused on delivering high-performance coprocessors and boards to be used alongside general-purpose processors in the world's most compute-intensive applications. ClearSpeed recently demonstrated the Advance™ board, (which contains two CSX600s) on a standard system which increased the performance by 4x to 30.2 Gigaflops sustained LINPACK while reducing the overall power by about 10 percent compared to running the system on its own. The Advance board is targeted at data-intensive applications in such areas as financial, life sciences, computational chemistry, biology and computer-aided design for fluid dynamics.
"ClearSpeed is delivering some very impressive products in terms of enabling high-performance processing while solving the heat and power problem," remarks Brian Gardner, vice president of IP products at Denali, who adds that ClearSpeed's technology is amazing. "While our Databahn IP has been used successfully in wide range of applications, from handsets to enterprise servers, this is clearly one of the more interesting applications. Delivering this kind of performance is a testament to the quality and configurability of our IP products. We are proud to have ClearSpeed as a customer."
About Databahn
Licensed for use in more than 170 designs, and with more than 65 chips in production, Databahn is the industry-leading memory controller IP solution. Databahn cores offer configurability to deliver optimal performance for a wide range of end applications, and are silicon proven in more than 18 process nodes. To ensure compatibility with all the latest high-speed memory technologies, the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, GDDR3, and Mobile DDR-SDRAM devices from all major memory vendors. Deliverables include: register transfer level (RTL) and synthesis scripts, silicon-independent DDR PHY, verification testbench, static timing analysis (STA) scripts, programmable register settings and documentation. Databahn IP is library independent and covers solutions from .18-micron to .09-micron technologies, and DRAM device frequencies from 100-400MHz (200-800MHz data rate).
About Denali
Denali Software Inc. is the world's leading provider of Electronic Design Automation (EDA) and Intellectual Property (IP) products for design and verification of semiconductor chip interfaces. Denali's Databahn™ and Dataplex™ IP products provide control and optimal data throughput for external DRAM and Flash memory devices. The PureSpec™ and MMAV™ verification IP products support all standard interfaces, including DRAM, Flash, PCI Express, ASI, AMBA, USB, Ethernet, Serial ATA, and CE-ATA. Denali's Blueprint product provides complete solution for on-chip register design and management. For more information, visit Denali at http://www.denali.com, call (650) 461-7200 or email info@denali.com.
|
||||||
Related News
- Samsung Teams with Denali Software to Improve Memory System Design Process
- Freescale Selects Denali for DDR Memory System Deployment
- BroadLight Continues 3rd Generation of PON System Deployment Success With Denali DDR Memory System Solution
- ON DEMAND Microelectronics Selects Denali's Mobile DDR Memory System Solution for Latest Video Portable Devices
- Global Unichip Selects Denali for DDR Memory System Deployment
Breaking News
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- Keysom Unveils Keysom Core Explorer V1.0
Most Popular
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- Ceva, Inc. Announces First Quarter 2025 Financial Results
- Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
|
E-mail This Article | 
|
|
Printer-Friendly Page |