TaraCom Introduces SerDes/PHY IPs in 90 and 65-Nanometer

Santa Clara, Calif, July 6, 2006— A dramatic growth in storage systems for the Small Business and media for HD TV will be enabled by high performance the SerDes/ Phy technology.  The widespread demand for 65nm process illustrates that customers recognize the ability to obtain lower cost circuits, power savings and performance-enhancing helping to cut manufacturing costs and, ultimately, lower total cost of ownership for customers.  As power supply voltages drop so does the noise margin.  TaraCom  is applying advanced process technologies to a set of complex designs that move the storage, network, and communications industries forward.

TaraCom Integrated Products is a fabless semiconductor company pioneering high jitter performance SerDes and high speed I/O technology.   TaraCom has ported the Serial ATA (SATA) core intellectual core property (IP) for integration into SoC and ASIC designs ranging from XAUI compliant, PCS/PMD functionality of the 10 Gigabit Ethernet XAUI and 10 Gigabit Fibre Channel specs as well as SATA, PCI Express, XGMII and other related applications. 

TaraCom has ported its TaraCom III ™ SATA Phy IP core progressively from 130-90-65 nm process technologies for easy design integration. The 3 new IP products cover a broad family of SerDes mixed signal IPs capable of throughput rates from 1.0-6.25 Gbps custom-designed for standard  XAUI, PCI Express Gen 1 and 2, Infiniband & SONET and  SATA Phy Gen 1 and 2    The new TaraCom III ™ product family consisting of the following parts that will be available by October 2006.

• SATA Host Phy IP Core  
• XAUI SerDes Phy IP Core
• PCI Express IP Core 

Dr. Reza Gholami, VP System Engineering, indicated that this 3rd IP generation SerDes technology offers highest jitter tolerance similar to TaraCom’s predecessor IP products.   This enables the integration of the IP in SoC and ASIC in the presence of multiple high speed clocks and noisy environments.  The new 3rd generation solutions operate at 1 volt providing significantly reduced power consumption per channel over existing solutions. In their lowest power mode, the PHYs consume less than 75 mW of power per channel, which is 20% less than competitive products. Optimized low leakage solutions of 65 nm processes are being utilized in development of high speed SerDes and Phys thru extensive previous design activity...

Charlie Smaltz, Business Development Department will lead the sales and marketing activity on a worldwide basis. From a marketing viewpoint, he confirmed existing market research that indicated a rapid transition from the existing 130nm and 90 nm geometry to the 65 nm and should dominate industry standard in CY2007.  "The easy stuff people already do — things like high- and low-leakage cells, clock gating and multiple threshold voltages. The next stage is multiple power domains".  TaraCom offers “Shuttle support”, production test consultation or test development to support licensee’s requirements.