English
Ground shifting in multicore interconnect battleground
By Rick Merritt, Courtesy of EE Times
Oct 2 2006 (9:00 AM)
A battle royal is shaping up behind the scenes as Advanced Micro Devices Inc. and Intel Corp. race to define interconnects for their next-generation multicore processors. The archrivals hope to use those links to weave separate webs of partnerships that will be keys to success in tomorrow's computer industry.
Last week, a broad group of chip and systems makers led by Intel and IBM Corp. launched Geneseo, code name for a set of extensions to PCI Express that aim to help graphics chips and other accelerators plug directly into a coherent processor. The news, delivered at last week's Intel Developer Forum in San Francisco, came in the wake of AMD's June announcement that it would invite the industry to plug into its proprietary HyperTransport CPU bus as part of a new program dubbed Torrenza.
The interconnects are likely to become part of the secret sauce for both companies' future multicore architectures. The extent to which the two are able to court the industry to provide blocks that may plug into 16 (or more) core CPUs could be a make-or-break factor in the two companies' turf wars in 2010 and beyond.
The Geneseo proposals aim to extend Express in four broad areas, providing fine-grained power management, a locking mechanism for shared memory, hints to help a coherent processor handle I/O more effectively, and memory and protocol efficiencies for mapping virtual to physical memory. The group may develop additional proposals in the future.
The resulting improvements fall short of creating a cache-coherent version of Express; as such, they do not provide all the underpinnings offered by the coherent HyperTransport (cHT) technology at the heart of AMD's Torrenza program. Nevertheless, functionally the Express extensions aim to address many of the same core uses as Torrenza, including providing a standard connection between a pro- cessor and accelerators for functions that could include networking and XML processing.
Oct 2 2006 (9:00 AM)
A battle royal is shaping up behind the scenes as Advanced Micro Devices Inc. and Intel Corp. race to define interconnects for their next-generation multicore processors. The archrivals hope to use those links to weave separate webs of partnerships that will be keys to success in tomorrow's computer industry.
Last week, a broad group of chip and systems makers led by Intel and IBM Corp. launched Geneseo, code name for a set of extensions to PCI Express that aim to help graphics chips and other accelerators plug directly into a coherent processor. The news, delivered at last week's Intel Developer Forum in San Francisco, came in the wake of AMD's June announcement that it would invite the industry to plug into its proprietary HyperTransport CPU bus as part of a new program dubbed Torrenza.
The interconnects are likely to become part of the secret sauce for both companies' future multicore architectures. The extent to which the two are able to court the industry to provide blocks that may plug into 16 (or more) core CPUs could be a make-or-break factor in the two companies' turf wars in 2010 and beyond.
The Geneseo proposals aim to extend Express in four broad areas, providing fine-grained power management, a locking mechanism for shared memory, hints to help a coherent processor handle I/O more effectively, and memory and protocol efficiencies for mapping virtual to physical memory. The group may develop additional proposals in the future.
The resulting improvements fall short of creating a cache-coherent version of Express; as such, they do not provide all the underpinnings offered by the coherent HyperTransport (cHT) technology at the heart of AMD's Torrenza program. Nevertheless, functionally the Express extensions aim to address many of the same core uses as Torrenza, including providing a standard connection between a pro- cessor and accelerators for functions that could include networking and XML processing.
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