S1 Core, a 64-bit Wishbone-compliant CPU Core based upon the OpenSPARC T1 microprocessor, easily synthesized for Virtex-4

April 23, 2007 -- Arturo Mann proudly announces that he has successfully synthesized the S1 Core on a Xilinx Virtex-4 FPGA device.

The current build_xst script in the official S1 Core enviroment works with the free (as in beer) version of Xilinx ISE WebPack, and the default FPGA device selected by this script is the one embedded in the Xilinx Spartan-3E Starter Kit: it does not fit the whole S1 Core so the report you'll get will be as follows:

But with the commercial version of Xilinx ISE Foundation Arturo was able to select a Virtex-4 LX60 device, obtaining:

He was able to complete HDL compilation, synthesis, place-and-route and obtained a valid bitstream ready to be loaded onto the board.

If you want to test the S1 Core on your FPGA board just change the name of the device following the -p option embedded in the file $S1_ROOT/tools/src/build_xst.cmd before launching the build_xst script.

Learn more...
Go to S1 Core documentation page

Want the design?
Go to the Download Area

About Simply RISC
Simply RISC is a team of Italian engineers who have been working in the former Inmos group of STMicroelectronics in both Catania (Italy) and Bristol (UK), so the Simply RISC logo is a square Union Jack with Italian colors.

Simply RISC develops and supports CPU cores, peripherals and interfaces released under the GNU General Public License (GPL) to build complete designs of microprocessors, Systems-on-a-Chip (SoC) and Networks-on-a-Chip (NoC).

The first design released by Simply RISC is the S1 Core, a cut-down version of the OpenSPARC T1 processor that targets embedded devices such as PDAs, set-top boxes and digital cameras.