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MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5)
Xelic Announces Immediate Availability of 10Gb/s Ethernet Rate Adaptation IP Core
Rochester, NY -- April 25th, 2007 -- Xelic, Inc. today announced the immediate availability of their new 10Gb Ethernet Rate Adaptation Core (XCE10GA). The XCE10GA performs rate adaptation through the insertion and removal of complete PCS blocks containing idle characters to provide maximum transparency capability. Optional flow control is provided through the insertion of programmable PAUSE frames in open or closed loop configurations. 10GBASE-R and 10GBASE-W applications are supported with 64B/66B transmission codes transferred at a 10Gb rate using a 64-bit data bus operating at 161.13Mb/s. This core is intended as a host side OTN add-on for Ethernet support. The XCE10GA system side interface mates with the Xelic XCO2 Digital Wrapper framer core to provide a complete 10Gb OTN solution.
About Xelic
Xelic is a leading provider of networking intellectual property for FPGA and ASIC applications. Xelic was founded in January of 2002 and is located in Rochester, NY. For more information about Xelic, please visit www.xelic.com.
About Xelic
Xelic is a leading provider of networking intellectual property for FPGA and ASIC applications. Xelic was founded in January of 2002 and is located in Rochester, NY. For more information about Xelic, please visit www.xelic.com.
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