Aptix announces unprecedented 1.8 million gate block-based prototyping system

APTIX ANNOUNCES UNPRECEDENTED 1.8 MILLION GATE
BLOCK-BASED PROTOTYPING SYSTEM

New Interactive Software Simplifies the Emulation Process, Increases Predictability of Results

San Jose, CA - April 17, 2000 - Today, Aptix Corporation announced a new, block-based prototyping system that reduces the risk in developing system-on-chip (SoC) devices. The unique system, called SoC Explorer 2000™, represents both an increase in individual system emulation capacity (up to 1.8 million ASIC gates) and provides a new software environment that enables fast, efficient, and predictable SoC prototype creation directly from RTL designs.

SoC Explorer 2000 includes the new Expedition™ emulation software environment. Expedition simplifies mapping of RTL designs to prototype hardware by encapsulating logic synthesis, hierarchical partitioning, and co-emulation functions within an intuitive guide-mode graphical user environment to shorten the time-to-in-circuit operation. The Expedition software within SoC Explorer 2000 is a key element in realizing Aptix?s strategy of delivering easy-to-use, cost-effective tools for verifying SoC ASIC designs.

SoC Explorer 2000 is scalable, with a nominal rating of 1.8 million ASIC gates plus 5 Mbits of block memory per system. The proprietary hardware delivers in-circuit emulation speeds up to 20 MHz or higher. These large capacities and fast emulation speeds are made possible by the use of Xilinx Virtex™ 2000E FPGAs to provide the highest density block-based prototyping possible. Multiple systems can be combined to provide even greater verification capacity. Previous generation Aptix products have been used to verify designs as large as seven (7) million ASIC gates when multiple systems are combined in a single project.

Block-based prototyping accelerates system integration by enabling verification of IP block interaction and the debugging of embedded software. Performing verification of the RTL design description at hardware prototype speeds, while the project is still in the synthesis optimization and chip layout phase, saves many weeks of in-circuit post-silicon SoC debugging.

"Aptix is one of Xilinx's best partners currently utilizing the Virtex series of FPGAs. We are very pleased that they are one of the first to incorporate the Virtex-E family of devices with the V2000E FPGA in a prototyping system," stated Dennis Segars, Xilinx senior vice president and general manager. "The performance and flexibility delivered by these devices are important to the emulation industry in enabling them to continue to deliver leading-edge products to their customers in a timely and cost effective manner."

The unique Aptix block-based SoC prototyping methodology allows each RTL block to be mapped and verified against its test bench as an independent IP. This reduces the time to achieve full design in-circuit emulation, because the design mapping is performed in parallel with the hardware RTL design creation and simulation process. The resulting reconfigurable prototype of the design is used to integrate all design blocks and accelerate software integration and debugging. By identifying design problems early in the design cycle, sub-optimal fixes, usually in software, late in the development process are minimized.

"Aptix?s new Expedition software and the guide-mode interface will benefit our SoC ASIC development customers by helping them to get their new developers up to speed quickly, resulting in significant productivity gains," said Amr Mohsen, president and CEO of Aptix. "We expect our customers to get more reliable products to market far faster than with any other methodology."

About Aptix Corporation

Aptix Corporation?s products are used to verify system and system-on-chip (SoC) designs prior to integrated circuit (IC) and board tape-out and fabrication. Aptix?s products utilize the block-based verification methodology, which provides a mechanism to map and verify individual design blocks incrementally and in parallel with the design creation process. This methodology shortens the net prototype creation time to achieve real-world operation of the prototype to the few days required to map and verify the last RTL block designed. Debugging designs becomes simple because the mapping process is both under the user?s interactive control and follows the natural hierarchy of the design. This also makes tracing design problems back to the source netlist an intuitive process.

The company is privately held and is headquartered at 2880 North First Street, San Jose, Calif. 95134. Telephone (408) 428-6200, Fax (408) 944-0646. Visit Aptix on the Web at: http://www.aptix.com

###

System Explorer, SoC Explorer 2000, Expedition, Logic AggreGATEr, Module Verification Platform, MVP and Explorer are trademarks of Aptix Corporation.

Virtex is a trademark of Xilinx Corporation.

FOR MORE INFORMATION CONTACT:

LeAnne Frank Linda Lavin
Public Relations Marketing Communications
KVO, Inc. Aptix Corporation
503/221-7403 408/428-6297
leanne_frank@kvo.com lindal@aptix.com