OKI Turns to Cadence and the Open Verification Methodology (OVM) to Speed Product Development

OVM Enables OKI to Improve Verification IP Integration and Compress Testbench Development by 30%

SAN JOSE, Calif. -- 29 Jul 2008 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that the System Memory Business Division of Oki Electric Industry Co., Ltd. has adopted the Open Verification Methodology (OVM) to improve its verification process and speed development of its consumer-based portable device and computer peripheral device memory controllers. The new methodology streamlined OKI’s verification development leading to the creation of plug-and-play universal verification components (UVCs) for the company’s portable device host protocol, SPI, and memory interfaces using up to 30% less code than previous methods.

The OVM verification environment leveraged elements of OKI’s previous methodology to further reduce verification time and costs. The team also took advantage of the Cadence SimVision object-oriented debug capabilities in the Cadence® Incisive® Enterprise Simulator to identify bugs much earlier in the development process. The proven SystemVerilog-class based library within the OVM was easy to use, allowing the team to get up and running much earlier in the project. Overall the verification environment development time turned out to be far less time consuming and more predictable than OKI’s previous approach.

“Our team found the OVM and the SystemVerilog support in the Incisive Enterprise Simulator to be extremely robust on our production project,” said Hiroyuki Fukuyama, team manager, System Memory Business Division at OKI. “We were able to easily adopt the OVM to develop verification IP, and the expert help from our local Cadence application engineer further shortened our learning curve. We expect to scale our use of the OVM to other project teams in OKI, reducing the time and cost to verify our high-quality products.”

“Our customers require verification methodologies that are open and can scale to the system level and across project teams,” said Ziv Binyamini, corporate vice president at Cadence. “The OVM provides a unique architecture for developing reusable verification components that can address these needs, allowing industry leaders such as OKI to meet their verification closure demands.”

Open Verification Methodology
The Open Verification Methodology, based on IEEE Std. 1800™-2005 SystemVerilog standard, is the first open, language-interoperable, SystemVerilog verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. To download the OVM please go to www.ovmworld.org.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.