Mentor Graphics Announces Scalable TLM-2.0 Design Flow Using Vista and Catapult C Synthesis Electronic System Level (ESL) Design Tools

Unique single-model approach from concept-to-implementation

WILSONVILLE, Ore., January 20, 2008 – Mentor Graphics Corporation (NASDAQ: MENT) today announced a new Scalable Design Methodology based on a layered transaction level model (TLM) that allows a single model to be taken from design concept to implementation. The Mentor Graphics Vista™ family of electronic system level (ESL) design tools are structured to support an efficient “layered” modeling based on the recently announced SystemC Transaction-level Modeling Standard (TLM-2.0) by the Open SystemC Initiative (OSCI).

Mentor Graphics also announced an automated flow between the Catapult® C Synthesis tool and Vista offering a TLM wrapper generation flow which now supports TLM-2.0 compatible models. The Catapult-Vista TLM-2.0 model generation flow bridges the gap between hardware design and system-level modeling by providing a link between the Catapult C Synthesis tool untimed ANSI C++ source and the Vista SystemC scalable design and simulation environment. This provides an industry-first automated ESL design flow from high-level synthesis to models based on the TLM-2.0 standard.

The TLM-2.0 standard provides SystemC model interoperability and reuse at the transaction level, resulting in an ESL “framework” to validate system hardware, analyze system architecture and software execution, and link with the software development chain. While TLM-2.0 serves as a good basis for interoperability and extensions, Mentor has taken this technology a step further in modeling efficiency.

Using an object-oriented (OO) approach that separates functionality from communication, timing and power, the Vista design suite provides a single-model that can scale from a pure untimed functional model to a fully implemented one; thus, seamlessly link with both software domains and hardware implementation for optimized success, efficiency and reliability. This approach applies also for power modeling at the TLM level, for applications such as semiconductors for consumer electronics and mobile communications devices.

“Adoption of the TLM-2.0 standard protects the designer’s investment in high-level models,” stated Mike Meredith, president of OSCI. “We welcome the Mentor Vista product line to the growing industry support for TLM-2.0 which enables users to effectively integrate models and tools to create verification platforms needed for today’s highly advanced designs.”

“As the leading ESL technology solutions provider in the EDA industry, our goal is to enable the design community to be productive, innovative and meet their design challenges,” stated Simon Bloch, vice president and general manager of Mentor Graphics design and synthesis division. “By providing our customers with the Vista ‘single-model’ Scalable Design Methodology, we hope to encourage wider industry adoption of the TLM-2.0 standard.”

About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $850 million and employs approximately 4,450 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: www.mentor.com/.