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32Gbps, 31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
Duolog's Weaver breaks the SoC integration barrier
Dublin, Ireland -- July 14, 2009 - Duolog Technologies, the Collaborative Design Automation Company, has announced the release of Weaver, an EDA tool for chip assembly that forms part of the Socrates Chip Integration Platform. Weaver is used to quickly and efficiently package and integrate the IP components of a system using rules-based integration, a methodology that promotes a formal method for System-on-Chip integration.
“Weaver is the keystone of Duolog’s chip integration platform and, with it, we now offer the most comprehensive IP to chip-level integration flow on the market,” said David Murray, Duolog CTO. “Not only do we offer the largest range of chip integration applications, but our solutions in these areas are second to none.” The formalization underlying Weaver’s rules-based integration encompasses the standardization of IP metadata, powerful assembly primitives that manipulate the metadata and high-level integration functions that automate the different assembly tasks. This layered approach offers orders of magnitude more productivity than conventional methods employing manual connectivity.
“Unfortunately, Moore’s law has caught up with us, and today’s interfaces are like yesterday’s ports – there are still too many of them,” said Murray. “Hooking up chips manually is ineffective and error-prone. While we need more automation, ad-hoc scripting cannot deliver the levels of robustness and reusability that are required. We believe that Weaver achieves the perfect balance and offers a ‘formal but flexible” approach to support best-practice chip integration.”
In one example, Duolog demonstrated how Weaver was used to integrate a peripheral sub-system, consisting of 22 IPs. It took just 30 minutes to achieve 100% connectivity and generate 1500+ lines of correct-by-construction RTL code. Not only that, but the sub-system itself was 100% packaged and generated over 4,000 lines of IP-XACT code. All of this was done with just 10 rules, including one which auto-generated and connected an AHB read-mux.
Much of the Weaver functionality was inherited from Duolog’s ‘Spider’ tool – a Windows-only connectivity solution. Weaver now joins the Bitwise and Spinner tools as part of the Socrates Chip Integration Platform which fully supports IP-XACT. “We use IP-XACT as a data-interchange mechanism and we utilise the metadata supplied,” said Murray. “Within Weaver, we focus on the integration task at hand, abstracting the information to intuitive levels and providing the flexibility to accelerate the integration task. We can then export an IP-XACT view of the completed design.”
Live demonstrations of Weaver can be seen at the Design Automation Conference (DAC) from July 26-31, 2009, at the Moscone Centre, San Francisco. Duolog will be occupying Booth #2028, adjacent to the DAC Pavilion.
About Duolog Technologies:
Duolog Technologies, the Collaborative Design Automation Company, is an award-winning developer of EDA tools that enable the flawless and rapid integration of today’s increasingly complex SoC, ASIC and FPGA designs. Duolog’s Socrates Chip Integration Platform employs a modular and extensible suite of tools for I/O layer definition, IP packaging, assembly and register management. The Socrates tools, built on the Eclipse platform and supporting the IP-XACT standard, shorten design cycles, reduce costs and greatly improve design quality through their Perfect-By-Construction™ methodology.
www.duolog.com
“Weaver is the keystone of Duolog’s chip integration platform and, with it, we now offer the most comprehensive IP to chip-level integration flow on the market,” said David Murray, Duolog CTO. “Not only do we offer the largest range of chip integration applications, but our solutions in these areas are second to none.” The formalization underlying Weaver’s rules-based integration encompasses the standardization of IP metadata, powerful assembly primitives that manipulate the metadata and high-level integration functions that automate the different assembly tasks. This layered approach offers orders of magnitude more productivity than conventional methods employing manual connectivity.
“Unfortunately, Moore’s law has caught up with us, and today’s interfaces are like yesterday’s ports – there are still too many of them,” said Murray. “Hooking up chips manually is ineffective and error-prone. While we need more automation, ad-hoc scripting cannot deliver the levels of robustness and reusability that are required. We believe that Weaver achieves the perfect balance and offers a ‘formal but flexible” approach to support best-practice chip integration.”
In one example, Duolog demonstrated how Weaver was used to integrate a peripheral sub-system, consisting of 22 IPs. It took just 30 minutes to achieve 100% connectivity and generate 1500+ lines of correct-by-construction RTL code. Not only that, but the sub-system itself was 100% packaged and generated over 4,000 lines of IP-XACT code. All of this was done with just 10 rules, including one which auto-generated and connected an AHB read-mux.
Much of the Weaver functionality was inherited from Duolog’s ‘Spider’ tool – a Windows-only connectivity solution. Weaver now joins the Bitwise and Spinner tools as part of the Socrates Chip Integration Platform which fully supports IP-XACT. “We use IP-XACT as a data-interchange mechanism and we utilise the metadata supplied,” said Murray. “Within Weaver, we focus on the integration task at hand, abstracting the information to intuitive levels and providing the flexibility to accelerate the integration task. We can then export an IP-XACT view of the completed design.”
Live demonstrations of Weaver can be seen at the Design Automation Conference (DAC) from July 26-31, 2009, at the Moscone Centre, San Francisco. Duolog will be occupying Booth #2028, adjacent to the DAC Pavilion.
About Duolog Technologies:
Duolog Technologies, the Collaborative Design Automation Company, is an award-winning developer of EDA tools that enable the flawless and rapid integration of today’s increasingly complex SoC, ASIC and FPGA designs. Duolog’s Socrates Chip Integration Platform employs a modular and extensible suite of tools for I/O layer definition, IP packaging, assembly and register management. The Socrates tools, built on the Eclipse platform and supporting the IP-XACT standard, shorten design cycles, reduce costs and greatly improve design quality through their Perfect-By-Construction™ methodology.
www.duolog.com
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