MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
Standard Cells reducing leakage 40 to 60 times at 90 and 65 nm from Dolphin Integration
Meylan, France – March 03, 2011. The SESAME BIV (Battery Interface Voltage) library of Standard Cells with its Flip-Flop patented for Low Voltage operation, is the winners' choice to in-house libraries for low-power applications.
SESAME BIV can be applied for two different and complementary purposes:
- Direct Battery supply: using the SESAME BIV for synthesizing small logic blocks directly connected to the battery with no need for an intermediate regulator.
- Low Leakage islet: SESAME BIV is superior for synthesizing an always-on logic block - such as Real Time Clocks - by maintaining the leakage to a level lower than HVt-based libraries.
Highlights
Direct battery supply
- Functional from 1.1 V up to 3.6 V thanks to patented flip flops
- Simple implementation: islets directly powered by the external battery
- No need for dedicated regulator
Low Leakage features
- Leakage reduction of 40 to 60 times in typical process
- Possibility to remove regulators and their leakage
Consistent kit for a straightforward design-in
- Isolation cells
- Ultra Low Leakage Level Shifters
- Custom PVT support
Optimal Design for Yield
- Design methodology ensuring High-Yield circuits despite Mismatch
- Specification of OCV margins
Already celebrated at 180 nm and 130 nm SESAME BIV is being released for 90 nm and 65 nm designs.
Have a quick look at:
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/sesame
|
Dolphin Semiconductor Hot IP
Related News
- Dolphin Integration offers first standard cell library to enable a leakage reduction of 1/350 at 65 and 55 nm
- Leakage divided by more than 250 at 180 nm eLL with Dolphin Integration Panoply of memory and standard cells
- Dolphin Integration announce the availability of new ROM TITAN and ultra low leakage standard cell library SESAME BIV at TSMC 55 nm LP eFlash
- Disruption in library offering for the 90 nm LP process with Dolphin Integration's new generation of High Density Standard Cells
- Dolphin Integration introduces a new Panoply of Silicon IPs for reducing the 65 nm silicon area up to 10%
Breaking News
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- Keysom Unveils Keysom Core Explorer V1.0
Most Popular
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- SiFive and Kinara Partner to Offer Bare Metal Access to RISC-V Vector Processors
- Imagination Announces E-Series: A New Era of On-Device AI and Graphics
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |