Proven on silicon: A Panoply of Memories and Standard Cells of Dolphin Integration to divide dynamic power by 5 at 180 nm!

Grenoble, France -- November 28, 2011 -- With the release of its latest 180 nm Panoply of standard cells and memories, Dolphin Integration paves the way for a new generation of ultra low power SoCs in mature processes.

This panoply already celebrated at various foundries in diverse 180 nm flavors reaches TSMC, Silterra, Dongbu and now the EEPROM process at SMIC: it satisfies the stringent cost and power minimization for the MCU and wireless devices, as well as the needs of mobile phones and smart cards.

Dolphin Integration’s Panoply is based on a comprehensive set of silicon-proven products:

Single Port RAM generator
Standard Cell Library and associated Islet Construction Kit
Metal programmable ROM generator
Efficient Power Regulators

As the result of Dolphin’s 26 years’ low power expertise, this Panoply enables a power reduction by a factor of 5 compared with the other libraries available.

Highlights on the capabilities offered for SoC power sensitive architectures:

1. Low voltage operation

Down to 1.0 V
Dual Voltage variant of the Panoply also available

2. Safe integration and right-on-first pass silicon

Proven on silicon
Patented standard cell architecture
Proprietary methodology to validate the sRAM bit-cell SPICE model behavior at low voltage
SpRAM architecture specifically designed to limit dynamic IR Drop
Models of peak current delivered for free

3. Power islets

Low Power cells for power gating and state retention of logic blocks
Embedded power switches for partial or complete shut down of memory blocks
UPF/CPF compatibility

4. Reduced die cost

Standard Cell library compatible with 1P3M SoC implementation
For memories, deliverables are compatible with Top Metals 4 or 5 or +

Have a quick look at the Presentation Sheets of these products:

For requiring an access to the online memory generators, please click here

About Dolphin Integration

Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/ragtime