Dolphin Integration unveils an sRAM architecture for Cost Sensitive Devices at 90 nm LP

Grenoble, France – December 16, 2011. Dolphin Integration is releasing RHEA, the latest innovation of the sRAM family, for cost sensitive SoCs at 90 nm and 85 nm TSMC technological processes.

In view of users’ requirement of higher density, the SpRAM RHEA achieves just that, with a reduction up to 10%, for any memory instance. What is much more, RHEA features the capability to operate down to 0.9 V ± 10% at 90 nm LP process.

The SpRAM RHEA not only provides the best combination of logic density and power consumption:

up to 10% denser than traditional memory compiler
up to 50% less consuming than traditional memory compiler at nominal voltage, but RHEA also includes crucial functionalities:
low voltage operation down to 0.9 V ± 10% for additional power savings
a data retention mode for ultimate leakage savings
choice of form factor thanks to multiplexing

“RHEA will enable Dolphin Integration to provide Customers with new capabilities for designing differentiated circuits at 90 nm LP in key markets for consumer devices, such as Flash controller market and Bridge Interface market”, said Elsa BERNARD-MOULIN, Dolphin Integration Marketing Manager for Libraries.

“RHEA is welcomed by our Users as the latest innovations embedded in this new RAM architecture raise their RoI to top-levels”

Availability:

The SpRAM RHEA generator is available for free download and use for 85 nm LP Users. For more information go to:

http://www.design-reuse.com/sip/view.php?id=28024

At 90 nm LP, the FE generator of the SpRAM RHEA is available free-of-charge.

For more information go to:

http://www.design-reuse.com/sip/view.php?id=28023

About Dolphin Integration

Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own missing EDA solutions enabling Support Engineering with Application Hardware Modeling as well as early Power and Noise assessment, plus engineering assistance for Risk Control.