VLSI Plus announces an FPGA version of its 64-bit Second Generation MIPI CSI2 Receiver

Raanana, Israel, October 22, 2012: VLSI Plus, a leading provider of MIPI CSI2 compliant IP cores, today announced the availability of the SVRPlus-CSI2-F a 64 bit serial video receiver, supporting MIPI® CSI2 and extensions to CSI2 with up to 8 data lanes and two clock lanes, and outputting 1, 2 or 4 pixels per clock.

VLSI Plus (www.vlsiplus.com) is a boutique IP house, specializing in digital video and, in particular, in IP cores complying with MIPI® CSI2 and CSI3 Camera Serial Interface standard. VLSI Plus is the first CSI2 IP core vendor to get MIPI® IOL certificate. FPGA versions of its first generation CSI2 IP cores are extensively used by leading CMOS image sensor vendors for the production floor testing of their sensor modules.

Yoav Lavi, founder and CEO of VLSI Plus said: “image sensor technology has progressed rapidly in the last five years, and the top level image sensors being introduced today stretch the CSI2 performance beyond its limit. In response, MIPI® has expanded the specifications of the DPHY standard to 1.5Gbps per lane. In addition some vendors defined extended CSI2, using 8 data lanes.

This increased performance also implies higher processing requirements for the application processor, and higher throughput through the CSI2 Receiver IP. To answer these new trends and developments, we recently introduced the SVRPlus-CSI2-I for the ASIC market, and today we add the SVR-CSI2-F for the FPGA market. The new IP supports 8 data lanes, has an internal 64 bit bus, and can generate 1, 2, or 4 pixels per clock. With the SVRPlus-CSI2-F, users can handle sensors with 8 lanes, outputting 1.5Mbps per lane, at manageable clock frequencies of around 220MHz”

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