Algotochip Becomes Tensilica Design Center Partner
Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
SANTA CLARA, Calif. – March 25, 2013 –Tensilica, Inc. today announced that Algotochip has joined its Xtensions™ partner network and will offer design services that incorporate Tensilica’s DPUs (dataplane processor units). Algotochip now has access to Tensilica’s technology to help it market and deploy innovative solutions that will enable developers to get their Tensilica-based products to market faster.
“The digital solution we provide are unique to the individual customer and completely owned by that customer,” said Didier Boivin, Algotochip’s vice president of marketing. “Once we receive the C-code and test-vectors to verify it, Algotochip does all the work involved in creating a complete digital solution including all the necessary software and firmware for the Tensilica DPUs. The customer doesn’t have to learn any new tools and can focus on the product specification and algorithms – realizing the digital solution through our relationship.”
Algotochip’s patented approach can speed hardware and software design for SOCs (systems on chip) in as little as eight weeks. Algotochip guarantees that its SOC meets all the performance specifications made by the customers, and insures that it will be right the first time.
“We are delighted to add Algotochip to our design center partner program,” stated Chris Jones, Tensilica’s director of product marketing. “They have extensive expertise in many areas of chip design and can help customers get their chips to market much faster.”
About Algotochip
Algotochip is the industry’s first company to provide complete SoC GDSII from Algorithms written in behavioral C-code in weeks versus years with conventional design approach. The company’s patented approach provides many direct benefits to the customer going from time to market to design cost to lower power through proprietary power aware architecture design. The company is privately held and based in Sunnyvale, California, U.S.A. For additional information, please visit http://www.algotochip.com.
About Tensilica
Tensilica, Inc. is the leader in dataplane processor IP core licensing with over 200 licensees. Dataplane processors (DPUs) combine the best capabilities of DSPs and CPUs while delivering 10 to 100x the performance because they can be optimized using Tensilica’s automated design tools to meet specific and demanding signal processing performance targets. Tensilica’s DPUs power SOC designs at system OEMs and seven out of the top 10 semiconductor companies for designs in mobile wireless, telecom and network infrastructure, computing and storage, and home and auto entertainment. Tensilica offers standard cores and hardware/software solutions that can be used as is or easily customized by semiconductor companies and OEMs for added differentiation. For more information on Tensilica’s patented, benchmark-proven DPUs visit www.tensilica.com.
|
Related News
- Fraunhofer IIS Becomes Tensilica Authorized Design Center Partner
- Dream Chip Technology Becomes Tensilica System-on-Chip (SOC) Design Center Partner
- Wipro Becomes Tensilica Processor Core Design Center Partner
- Inomize Becomes TSMC Design Center Alliance Partner
- Inomize Becomes Newest Tensilica Design Center in Israel
Breaking News
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- Keysom Unveils Keysom Core Explorer V1.0
Most Popular
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- Ceva, Inc. Announces First Quarter 2025 Financial Results
- Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |