Cadence Incisive Enterprise Simulator Improves Low-Power Verification Productivity By 30%
SAN JOSE, Calif., 07 May 2013 - Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today introduced a new version of Incisive® Enterprise Simulator, with features that improve low-power verification productivity of complex SoCs by 30 percent. The 13.1 release of Cadence® Incisive Enterprise Simulator addresses low-power verification challenges for advanced modeling, debug, power format support and to provide faster verification for today’s most complex SoCs.
The new debug features in Incisive SimVision Debugger provide simple visualization and interactive debug of both complex text-based power intent standards. Other simulator enhancements include additional SystemVerilog support and faster elaboration to turn around simulation jobs much more quickly. Enhanced support for CPF and newly added support of IEEE 1801 will make these enhancements available to all low-power engineers.
“We successfully ran the Unified Power Format (IEEE 1801 / UPF) simulation with the Incisive Enterprise Simulator to identify power domains, verify isolation, and more,” said David Vincenzoni, R&D design manager at STMicroelectronics. “The tool works well and we applaud Cadence for adding the new advanced verification capabilities and IEEE 1801 support that will help speed the completion of our low-power SoCs.”
“As power demands grow with chip complexity, new low-power verification capabilities are required to adequately validate designs before they head to implementation,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “The latest release of Incisive Enterprise Simulator features new capabilities that ease the challenge of verifying all of today’s power-aware designs.”
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
|
Cadence Hot IP
Related News
- Intellitech iJTAGServer leverages Cadence Incisive Enterprise Simulator for IEEE 1149.1-2013 Silicon Instrument Verification
- Cadence and Arm Deliver First SoC Verification Solution for Low-Power, High-Performance Arm-Based Servers
- Cadence Announces Protium Rapid Prototyping Platform and Expands System Development Suite Low-Power Verification
- Cadence Incisive 13.2 Platform Sets New Standard for SoC Verification Performance and Productivity
- New Release of Cadence Incisive Platform Doubles Productivity of SoC Verification
Breaking News
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- Keysom Unveils Keysom Core Explorer V1.0
Most Popular
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- SiFive and Kinara Partner to Offer Bare Metal Access to RISC-V Vector Processors
- Imagination Announces E-Series: A New Era of On-Device AI and Graphics
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |