Synopsys Introduces Dolby MS11 Decoder for DesignWare ARC Audio Processors

Support for Dolby Laboratories' Multistream Decoding Expands Portfolio of ARC Audio Codecs

MOUNTAIN VIEW, Calif., Aug. 12, 2013 -- Synopsys, Inc. (Nasdaq: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the availability of the Dolby® MS11 Multistream Decoder optimized for its DesignWare® ARC® AS211SFX and AS221BD audio processors. The MS11 Multistream Decoder provides television and set-top box manufacturers with a single-package technology solution for decoding all premium audio formats, including Dolby Digital Plus, Dolby Digital, Dolby Pulse (AAC LC, HE AAC, and HE AAC v.2). The Dolby MS11 decoder has been certified by Dolby Laboratories for the ARC AS2xx family of single- and dual-core audio processors, allowing Synopsys to offer a complete and proven solution that simplifies the development, testing and qualification of Dolby MS10/MS11-enabled devices while ensuring optimal compatibility with the worldwide installed base of home theater systems and future broadcast audio standards.

"Dolby is committed to providing the best technology solutions to ensure maximum efficiency, consistency, and compatibility for the diverse needs of the global broadcast ecosystem," said Mathias Bendull, senior director for broadcast consumer audio at Dolby Laboratories. "With Dolby MS11, the DesignWare and ARC audio processors will enable Synopsys's customers to deliver a richer, high-quality sound experience in their audio-enabled devices."

Synopsys' DesignWare ARC audio solution is a scalable hardware and software IP solution that includes codecs, audio processors, media streaming frameworks and post-processing software. The Dolby MS11 decoder for ARC can be used on either a single-core AS211SFX or dual-core AS221BD ARC audio processor, which gives designers the flexibility to configure designs for specific applications and performance requirements. ARC audio processors incorporate dual MAC (Multiply-Accumulate) execution units for efficient audio processing, resulting in a processor load as low as 56 MHz for 100 cycles of latency from system memory and leaving sufficient bandwidth for additional audio software. Additionally, the ARC-optimized Dolby MS11 decoder enables a wide range of post-processing capabilities by including full access to the decoded audio streams. One key application is the ability to apply Dolby Volume to a decoded 5.1 Dolby Digital Plus stream and then re-encode the stream to Dolby Digital for output to a home theater. Synopsys' entire family of DesignWare ARC audio codecs is optimized for performance and ease of integration into SoCs and is fully compliant to audio industry standards such as AMR-WB+, MPEG-4 aacPlus v2, FLAC, WMA 10 Pro, Dolby Digital Plus and DTS-HD Master Audio.

"The growth in available ARC audio codecs demonstrates the scalability of our end-to-end DesignWare ARC Audio solution and our support for the latest audio technologies," said John Koeter, vice president of marketing for IP and systems at Synopsys. "Availability of Synopsys' Dolby MS11 decoder software for DesignWare ARC audio processors continues the expansion of our audio IP portfolio and provides IC and consumer product manufacturers with a single certified decoder that reduces the complexity and cost of integrating multiple audio technologies into new receivers."

Availability and Resources

The Dolby MS11 decoder, optimized for the AS211SFX and AS221BD audio processors, is available now.

Learn more about the Dolby MS11 Encoder for ARC audio processors: http://www.synopsys.com/dw/ipdir.php?ds=arc_audio_dolby_ms11
Learn more about the DesignWare ARC audio solution: http://www.synopsys.com/IP/ProcessorIP/ARCAudio/Pages/default.aspx

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries, processor cores and subsystems. To support software development and hardware/software integration of the IP, Synopsys offers drivers, transaction-level models, and prototypes for many of its IP products. Synopsys' HAPS® FPGA-Based Prototyping Solution enables validation of the IP and the SoC in the system context. Synopsys' Virtualizer virtual prototyping tool set allows developers to start the development of software for the IP or the entire SoC significantly earlier compared to traditional methods. With a robust IP development methodology, extensive investment in quality, IP prototyping, software development and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: http://www.synopsys.com/designware.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at http://www.synopsys.com.