Yield And Reliability Issues With Integrating IP

Ed Sperling, Semiconductor Engineering
December 12th, 2013

First of three parts: Why IP doesn’t always work as planned; the most common causes of re-spins; factors that can affect IP integration and why some tests don’t always reveal problems.

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation.