eInfochips improves reliability for avionics systems with new ARINC 429 Verification IP
New ARINC 429 VIP accelerates test-bench development for reliable communication interfaces for avionics systems
Ahmedabad -- March 23, 2015 -- eInfochips, a leading product engineering services company, today announced the availability of the new eInfochips ARINC 429 Verification IP (VIP). ARINC (Aeronautical Radio Incorporation) defines the standard requirements for transfer of digital data between avionics systems for commercial and transport aircraft. Companies designing next generation aircraft data and communication products can improve reliability and performance with the new eInfochips ARINC 429 VIP. The ARINC 429 VIP, coupled with eInfochips VLSI Verification Services will accelerate RTL verification cycles for standards compliant avionics systems.
Parag Mehta, Chief Marketing and Business Development Officer at eInfochips said, “Our customers are always looking for faster and better ways to design next-gen systems. We continue to support this endeavour with accelerators such as the eInfochips ARINC 429 VIP. Our ARINC 429 VIP emphasizes our commitment to the aerospace industry.” Aerospace is one of the largest practices at eInfochips, with services for DO-254, DO-178B/C and DO-160. The company has engagements with 5 of the Global Top-10 commercial aerospace companies.
ARINC 429 employs multiple physical, electrical and protocol techniques to minimize electro-magnetic interference with on-board radio communications and other transmission lines. The eInfochips ARINC 429 VIP is compliant to ARINC Specification 429 Part 1 to Part 18 (429P1-18). It is implemented in SystemVerilog with UVM methodology environment. The eInfochips ARINC 429 VIP deliverables include the UVM Source Code, Product Documentation and Sample Test Cases. A full datasheet of the ARINC 429 VIP is available for download.
eInfochips VIP Development and Verification Practice
eInfochips has developed 32 complex VIPs for top global EDA companies and end-customers. Their experience includes VIPs for the latest high-speed and low-power protocol standards, like MIPI, USB 3.0, DDR3, HDMI and eMMC. Today, eInfochips has contributed to VIPs deployed by hundreds of engineers for ASIC, SOC and FPGA designs.
At SNUG 2015 (Santa Clara, CA) this week, eInfochips will showcase Verification and Custom VIP Services. Interested companies can schedule a meeting with eInfochips, or contact marketing@einfochips.com for more details.
About eInfochips
eInfochips is a global product innovation partner recognized for technology leadership by Gartner, Frost & Sullivan, NASSCOM and Zinnov. eInfochips has contributed to 500+ products for top global companies, with more than 10 million deployments across the world.
|
Related News
- eInfochips shortens verification cycles and improves reliability for ASIC and SoC designs with Verification IPs
- eInfochips improves reliability for automotive components with CAN 2.0 Verification IP
- eInfochips PCIe Verification IP enables reliability for high-speed computing
- New AXI4 VIP Suite to improve FPGA and SoC reliability for ARM-based designs
- Microsemi and eInfochips Collaborate to Improve Efficiency, Reliability and Performance for Critical Avionics Systems Development and Design
Breaking News
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- Keysom Unveils Keysom Core Explorer V1.0
Most Popular
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- SiFive and Kinara Partner to Offer Bare Metal Access to RISC-V Vector Processors
- Imagination Announces E-Series: A New Era of On-Device AI and Graphics
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |