MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
Omnitek announce availability of IP for SDI I/O, SDI Gearbox and SDI Standards Conversion for Xilinx FPGAs
BASINGSTOKE, UK. November 14, 2016 – Omnitek - a well-established provider of video IP and design services vendor, is today announcing the release of SDI I/O Subsystem IP, SDI Gearbox IP and SDI Standards Conversion IP for Xilinx FPGA design.
Omnitek SDI I/O Subsystem IP supports transmit and receive for a wide range of SD, HD, 3G, 6G and 12G video standards. This includes multi-link standards such as 2160p60 over quad link 3G-SDI in level A or B and in Square Division or 2SI modes; Dual link 6G-SDI and 12G-SDI. In total, over 1,700 formats are supported.
The IP is highly optimised for minimal resource count and is supplied with drivers and application examples. Full details can be seen here.
Building upon the SDI I/O Subsystem IP, Omnitek is also announcing the availability of SDI Gearbox IP. This supports conversion between multiple SDI link formats including Quad 3G-SDI conversion to and from 12G-SDI.
The Gearbox IP supports two further optional extensions. The first extension facilitates the support of Square Division SDI modes. So, for example, Quad 3G-SDI level A or B Square Division can be converted to or from 12G-SDI, or Quad 3G 2SI video standards.
By combining with Omnitek OSVP IP, the Gearbox IP can be further extended to support full standards conversion between all supported SDI standards. Details of the OSVP IP can be seen here.
All this IP has been used in multiple video product designs, including Omnitek’s Ultra 4K Toolbox range.
At InterBEE 2016 (November 14th-16th), Omnitek will be demonstrating this IP on the Image Matters booth. The Ultra 4K Tool Box will be demonstrated on the Photron and Techno-House booths. Omnitek CEO, Roger Fawcett, will be attending InterBEE and will be available to discuss you product design.
|
Related News
- Xilinx Announces General Availability of Virtex UltraScale+ FPGAs in Amazon EC2 F1 Instances
- Lattice FPGAs with High I/O Density Bring Low Power Signal Bridging and Interface Management to Edge Devices
- OmniPhy Announces 2.5v I/O Transistor based Mixed Signal PHY Availability in TSMC 28nm HPM
- Xilinx Announces Industry's First Dual 100 Gbps Gearbox Solution for Interfacing CFP2 Optical Modules to Virtex-7 HT FPGAs
- Xilinx Ships Virtex-5 FXT FPGAs, Delivering the Ultimate in System Integration for Designs That Demand High-Performance Processing and High-Speed Serial I/O
Breaking News
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- Keysom Unveils Keysom Core Explorer V1.0
Most Popular
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- SiFive and Kinara Partner to Offer Bare Metal Access to RISC-V Vector Processors
- Imagination Announces E-Series: A New Era of On-Device AI and Graphics
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |