sureCore Delivers Customised Low Power SRAM for Data Intensive Designs
New SureFit service customises memory for Imaging, Artificial Intelligence and Machine Learning Applications
SHEFFIELD, England, March 21, 2019 -- sureCore Limited's new SureFit SRAM customization service has delivered low power high capacity SRAM subsystems implemented in advanced FinFET processes to Tier-1 players in the demanding imaging, artificial intelligence and machine learning markets.
The SureFit developed memory system integrates very large memory arrays, delivering high bandwidth, low latency and multi-port capabilities required by these data intensive applications. It builds on sureCore's patented power saving technology that provides both functional and power optimised memories to deliver unprecedented dynamic and static power savings for multi-megabyte, on-chip SRAM arrays.
"SureFit memories deliver power efficiencies by coupling custom innovative low power single port memories tiled in an array with energy efficient interconnect and intelligent memory subsystem control. The result is pseudo multi-port operation with minimum area, dynamic power and leakage," said Paul Wells, CEO.
By engaging with leaders across a broad range of markets, sureCore has developed bespoke solutions tailored to meet precise application demands that have delivered up to 70% power savings.
"AI/ML investments exceeded $19 billion in 2018. A key facet of these applications is the integration of large multi-port SRAMs. For many edge devices, off-the-shelf solutions don't deliver the necessary power efficiencies. Current customer engagements are a testimony to SureFit's ability to provide custom, optimised memory solutions tailored to precise specifications," Wells said.
Delivering competitive and differentiated power efficient solutions means addressing the memory subsystem design. Adopting a bottom-up custom design strategy enables closer alignment with the system architecture resulting in a more power and feature-optimised solution.
Laying out a roadmap for future developments Wells commented that, "We are actively exploring integrating computational elements within the memory subsystem to further increase processing capacities and cut power budgets."
Delivering competitive products in this space necessitates a holistic approach to system level considerations. As Wells puts it, "Low power SRAM is no longer just low power SRAM!"
For additional information, go to www.sure-core.com
About sureCore
sureCore Limited is an SRAM IP company based in Sheffield, UK, developing low power memories for current and next generation, silicon process technologies. Its award-winning, world-leading, low power SRAM design is process independent and variability tolerant, making it suitable for a wide range of technology nodes. This IP helps SoC developers meet challenging power budgets and manufacturability constraints posed by leading edge process nodes.
|
Related News
- SureCore announces low power cryogenic memory technology that could help dramatically cut data centre power usage
- Surecore's Low Power Memory Delivers Improved Power Efficiency For BLE-Enabled Devices
- sureCore PowerMiser Low Power SRAM IP Now on Samsung 28nm FDS Process Technology
- sureCore Unveils Low Power Design Service
- sureCore Opens Low-Power SRAM IP Customization Service
Breaking News
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- Keysom Unveils Keysom Core Explorer V1.0
Most Popular
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- Ceva, Inc. Announces First Quarter 2025 Financial Results
- Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |