TriCN to preview next-generation, all-digital Serdes "engine" at DesignCon 2003

New TriDL G2 Technology Delivers Up to 5 Gigabit/second Throughput in Support of Maximum Performance for PCI Express and XAUI Multi-Gigabit Interfaces

SAN FRANCISCO, CA –January 27, 2003 –TriCN, a leading developer of intellectual property (IP) for high-speed interface technology, today announced the introduction of its groundbreaking Serializer/Deserializer [SerDes] technology, named TriDL G2 (Digital Dynamic Deskewing Link). TriDL G2 is an ultra high-performance I/O interface "engine" that is capable of delivering up to 5 Gigabit/second throughput with significantly lower power and area requirements than comparable analog solutions. The TriDL G2 SerDes will serve as the core, underlying technology for TriCN's upcoming introduction of PCI Express and XAUI interface products.

"TriDL's all-digital implementation is a dramatic departure from the competition", explains Ron Nikel, Chief Technology Officer with TriCN. "The all-digital approach not only provides savings in area and power usage, but also streamlines porting and testability, and offers increased noise immunity not found in analog based devices. This is a powerful and unique combination of features that will be extremely attractive to designers of high performance semiconductors used in communications, networking, data storage and memory markets."

The TriDL G2 architecture consists of a transmitter hard macro, and a receiver hard macro. The modular design of the TriDL G2 SerDes allows semiconductor developers to integrate the TriDL G2 SerDes IP in bundles of 1 to 32 lanes, yielding as much as 320 Gb/s aggregate data rates, sufficient to meet even the most aggressive throughput requirements.

TriDL G2 employs TriCN's unique, patent-pending approach to skew compensation, for maximum skew tolerance and unprecedented throughput levels. Offering a dynamic alignment approach to skew compensation, it provides bit-level de-skewing that delivers up to 24UI of skew compensation at 5Gb/s per lane. This is performed without the use of a delay-locked loop (DLL), thereby affording semiconductor designers significant savings in silicon area over comparable analog DLL-based implementations. Area requirements for TriDL G2 are .12mm² per lane.

By eliminating the need for a DLL, TriDL G2 also functions with dramatically lower power requirements compared to analog solutions. Typical combined power requirements for TriDL G2's transmitter and receiver are 24 mW per lane.

Availability
TriCN's TriDL G2 has been targeted for Taiwan Semiconductor Manufacturing Company's (TSMC) 0.13um process, and will be made available in conjunction with the introduction of TriCN's PCI Express and XAUI products beginning inQ2 of 2003.

About TriCN
Founded in 1997, San Francisco, California-based TriCN is a leading developer of high- performance semiconductor interface intellectual property (IP). The company provides a complete portfolio of IP for maximizing data throughput on and off the chip. This IP is designed for IC developers addressing bandwidth-intensive applications, in the communications, networking, data storage, and memory space. TriCN's customers range from startup to established fabless semiconductor and systems companies, including Philips, MIPS Technologies, SGI, IBM, Cognigine, Internet Machines, and Apple Computer.

For more information, please visit TriCN's web site at www.tricn.com.

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