CORE-v CVE4 RTL Freeze Milestone Achieved

December 14, 2020 -- The OpenHW CV32E40P RISC-V core is the first open-source core for high-volume chips verified with the state-of-the-art process required for high-integrity, commercial SoCs.

The RTL Freeze milestone was achieved with OpenHW ecosystem contributors working collaboratively using CORE-V-VERIF, an OpenHW Group project to develop, deploy, and execute pre-silicon functional verification of the OpenHW Group’s CORE-V family of RISC-V cores. The CVE4, which is part of the CORE-V open-source IP family, matches the quality of IP offered by established commercial providers and is verified with state-of-the-art, auditable flows.

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CORE-V-VERIF provides a silicon-proven, industrial-grade functional verification platform to the RISC-V community. CORE-V-VERIF leverage verification components developed by the RISC-V community and will be continuously maintained and enhanced to integrate the latest best-practices and technology for the verification of future CORE-V cores.

CORE-V-VERIF includes verification strategy and planning documents, and SystemVerilog/UVM code implementing an end-to-end simulation environment. Additionally, the platform supports an advanced SVA formal verification environment, which leverages the RISC-V ISA specification in SAIL and provides optimal integration with simulation. The platform supports the use of structural, functional, and mutation coverage metrics and CORE-V-VERIF leverages both open-source and commercial IPs and EDA technology.

The CORE-V-VERIF project is hosted in the OpenHW Group GitHub repositories and is available to the community under the Solderpad 2.0 license.

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