Hardent Joins Samsung SAFE IP Partner Program & Launches New Display IP Subsystem Solution in Collaboration with Rambus
MONTREAL, May 25, 2021 -- Hardent, a leading provider of video compression IP cores, today announced it has joined the Samsung Advanced Foundry Ecosystem™ (SAFE™) as a member of the IP Partner Program. Samsung Foundry customers can now take advantage of Hardent's VESA® Display Stream Compression (DSC) IP cores as part of a new display IP subsystem solution offered in collaboration with Rambus.
The SAFE IP Partner Program is a key part of the Samsung Advanced Foundry Ecosystem (SAFE) that aims to create a strong ecosystem between Samsung Foundry and IP partners. The program provides diverse IP portfolios in various application fields, based on customer requirements.
The VESA DSC standard was developed by the Video Electronics Standards Association (VESA) for use in display applications where visually lossless, ultra-low latency compression is required. The DSC algorithm increases overall transmission bandwidth by up to 3X, allowing designers to achieve higher resolution displays on transport interfaces such as the MIPI® Display Serial Interface (MIPI DSI®).
Hardent's VESA DSC Encoder IP has been integrated with the Rambus MIPI DSI-2 Host Controller IP and Samsung C / D-PHY IP to form a complete display IP subsystem solution for designing next-generation displays. The three IP blocks together support a wide range of operation modes and have been fully optimized for performance in applications such as mobile, AR/VR, and automotive.
"We are honored to be a SAFE member and work with fellow SAFE IP Partner Rambus to deliver a new display IP subsystem tailored to the Samsung foundry process technologies," said Alain Legault, VP of IP Products at Hardent. "Samsung customers can now confidently integrate video compression into their SoC designs and accelerate their project timeline with this proven IP solution."
"We are pleased to have Hardent join the SAFE program as an IP partner," said Jongshin Shin, Vice President of Foundry IP Development Team at Samsung Electronics. "The new IP subsystem from Hardent and Rambus, combined with Samsung C/D-PHY IP, offers our customers a unique solution devised for seamless integration with the Samsung foundry processes."
"Initiatives like the SAFE program are important to meeting the demand for seamless integration of IP in advanced SoCs," said Matt Jones, General Manager, IP Cores at Rambus. "Our partnership with Hardent and Samsung allows customers to achieve the performance needed for next-generation displays with an integrated MIPI solution that reduces implementation risk and speeds time to market."
The MIPI DSI-2 / VESA DSC host IP subsystem from Hardent and Rambus offers:
- A dual channel MIPI DSI-2 Transmitter with DSC Compression including a:
- Hardent DSC v1.2a Encoder IP
- Rambus DSI-2 Host Controller
- Samsung Foundry C/D-PHY Combo - Dual Channel
- Uncompressed & DSC compressed video transmission supported across one or two links
- Support for an asynchronous pixel source (from DMA) or synchronous pixel source (parallel video)
- Low power features
- SRAM sharing to reduce silicon area
The MIPI DSI-2 / VESA DSC host IP subsystem for Samsung Foundry customers is available now.
About Hardent
Hardent is a professional services firm providing engineering services, training solutions, and IP products to leading electronics equipment and component manufacturers throughout the world. For more information, visit http://www.hardent.com.
|
Related News
- QuickLogic Joins Samsung SAFE IP Partner Program
- Agnisys Joins Arm Partner Program and Releases Solution Brief for Functionally Safe Arm-Based SoC Design
- CEVA Joins Samsung SAFE™ Foundry Program to Accelerate Chip Design for the Mobile, Consumer, Automotive, Wireless Infrastructure and IoT Markets
- Silicon Frontline Accepted as Partner in Samsung Foundry SAFE™ Program
- Mixel, Rambus and Hardent Collaborate to Deliver State-of-the-Art Integrated MIPI Display Subsystem Solution
Breaking News
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- Keysom Unveils Keysom Core Explorer V1.0
Most Popular
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- SiFive and Kinara Partner to Offer Bare Metal Access to RISC-V Vector Processors
- Imagination Announces E-Series: A New Era of On-Device AI and Graphics
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |