TSMC Introduces N4X Process
Newest 5nm Enhancement Tailored for High Performance Computing Products
HSINCHU, Taiwan, R.O.C., Dec. 16, 2021 – TSMC (TWSE: 2330, NYSE: TSM) today introduced its N4X process technology, tailored for the demanding workloads of high performance computing (HPC) products. N4X is the first of TSMC’s HPC-focused technology offerings, representing ultimate performance and maximum clock frequencies in the 5-nanometer family. The “X” designation is reserved for TSMC technologies that are developed specifically for HPC products.
Leveraging its experience in 5nm volume production, TSMC further enhanced its technology with features ideal for high performance computing products to create N4X. These features include:
- Device design and structures optimized for high drive current and maximum frequency
- Back-end metal stack optimization for high-performance designs
- Super high density metal-insulator-metal capacitors for robust power delivery under extreme performance loads
These HPC features will enable N4X to offer a performance boost of up to 15% over N5, or up to 4% over the even faster N4P at 1.2 volt. N4X can achieve drive voltages beyond 1.2 volt and deliver additional performance. Customers can also draw on the common design rules of the N5 process to accelerate the development of their N4X products. TSMC expects N4X to enter risk production by the first half of 2023.
“HPC is now TSMC’s fastest-growing business segment and we are proud to introduce N4X, the first in the ‘X’ lineage of our extreme performance semiconductor technologies,” said Dr. Kevin Zhang, senior vice president of Business Development at TSMC. “The demands of the HPC segment are unrelenting, and TSMC has not only tailored our ‘X’ semiconductor technologies to unleash ultimate performance but has also combined it with our 3DFabric™ advanced packaging technologies to offer the best HPC platform.”
TSMC’s HPC platform not only offers performance-optimized silicon with N4X technology, but also provides the greatest design flexibility with its comprehensive 3DFabric™ advanced packaging technologies and a broad design enablement platform with our ecosystem partners through the TSMC Open Innovation Platform®.
For more information on the N4X process, please visit https://performance.tsmc.com
|
Related News
- eMemory introduces more security features to its eNVM IP for TSMC 7nm Process
- Arasan Chip Systems Introduces First eMMC v5.0 I/O PADs & PHY IP using TSMC 28nmHPM Process
- Synopsys Introduces Validated USB 2.0 nanoPHY IP for TSMC'S Nexsys 90-LP Process
- Cadence and TSMC Advance AI and 3D-IC Chip Design with Certified Design Solutions for TSMC's A16 and N2P Process Technologies
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
Breaking News
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- Keysom Unveils Keysom Core Explorer V1.0
Most Popular
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- Ceva, Inc. Announces First Quarter 2025 Financial Results
- Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |