Altera FPGA Enables Industry's Highest Source-Synchronous Data Transfer Rate

Stratix GX Device with Embedded DPA Circuitry Is Industry's Only FPGA Supporting 1-Gbps SPI-4.2 Signaling

San Jose, Calif., May 20, 2003-- Altera Corporation (NASDAQ: ALTR) today announced that its Stratix™ GX FPGA enables up to 1-Gbps SPI-4.2 performance, the maximum data rate (16-bit full-duplex) currently available using the source-synchronous differential I/O standard. The Stratix GX device family, with its embedded dynamic phase alignment (DPA) circuitry, is capable of delivering 25 percent faster performance than that offered by the nearest competing FPGA. A 25 percent increase in the data transfer rate of a carrier's multi-service switch or router can significantly reduce latency and improve quality of service.

The system packet interface (SPI-4.2) protocol is used in wireline telecommunications and networking equipment applications, such as central access switching, network core access routers, wide area network (WAN) routers and switches, and storage area network (SAN) switches. The SPI-4.2 protocol specifies a minimum 622-Mbps transfer rate on the 16-bit data interface. Interfaces between physical (PHY) layer and link layer devices typically operate at 700 to 800 Mbps, and the interconnect to the switch fabric operates at up to 1.6 times the line rate, or 1 Gbps for 10-Gbps line rate applications such as OC-192 packet over SONET (POS), 10 Gigabit Ethernet, or multi-channel Gigabit Ethernet.

By embedding the DPA circuitry directly in the silicon's source-synchronous channels, Stratix GX devices provide a verified, reliable solution for both skew reduction and higher speed data transmission. A soft DPA implementation, by contrast, ties up valuable logic resources, can rapidly consume a device's global clocks and phase-locked loops (PLLs), and tends to become error-prone in the face of process, voltage, or temperature changes. Embedded DPA circuitry avoids these problems and delivers error-free data transmission.

"As high speed interfaces with source-synchronous clocking schemes reach 1-Gbps data transfer rates, the margins for skew contract significantly," said David Greenfield, senior director of product marketing at Altera. "DPA circuitry meets this challenge by aligning a sampling clock with the incoming data. Soft DPA schemes are less reliable and cannot support 1-Gbps data transfer rates."

The Stratix GX device leverages Altera's extensive experience with source-synchronous differential I/O standards, which began with the APEX^™ device family over three years ago. It also leverages the company's SPI-4.2-compliant POS-PHY Level 4 MegaCore^® function, which is currently available for the Stratix GX device. A core license lists for $17,995.

About the Stratix GX Device Family
The Stratix GX family is Altera's second-generation embedded transceiver family based on a 0.13-micron process technology with 1.5-V core voltage. Stratix GX devices have up to 20 embedded 3.125-Gbps transceivers and up to 45 differential I/O pins with dedicated DPA capability supporting up to 1-Gbps source-synchronous data transfers. For more information about the Stratix GX device family, visit www.altera.com/products/devices/stratixgx/sgx-index.jsp.

About Altera
Celebrating its 20th anniversary this year, Altera Corporation (NASDAQ: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at www.altera.com.

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