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Duet Package of Embedded Memories and Logic Libraries for SMIC (65nm, 40nm)
Intel, TSMC to detail 2nm processes at IEDM
By Peter Clarke, eeNews Europe (October 8, 2024)
Intel’s attempts to get back to the leading-edge in chipmaking and foundry TSMC’s steps defining that leading-edge will be on show at this year’s International Electron Devices Meeting (IEDM) coming up in December, in San Francisco.
In a late news paper, researchers from TSMC will unveil the N2 manufacturing process, which is a nominal 2nm process designed for computing in AI, mobile and high-performance computing. In the following paper in the same session Intel engineers will provide details of scaling RibbonFETs, the name Intel gives to its nanosheet transistors.
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