MorethanIP releases the industy's first Fibre Channel FC-1/FC-2 cores with Gigabit and 2-Gigabit support for programmable logic devices

Karlsfeld - August 5, 2003 - MorethanIP today announced the immediate availability of the industry's first IP (Intellectual Property) solution for 1 and 2 Gigabit Fibre Channel applications. MorethanIP's Fibre Channel Core library includes Cores, which can be used independently or combined together to provide higher integration and lower cost solutions compared to existing implementations. The Cores can be targeted to Altera Stratix, StratixGX and Cyclone programmable logic devices and lower cost Hardcopy or ASIC devices.

The programmable 1 and 2 Gigabit Fibre Channel Transport Core implements Fibre Channel lower FC-1 and FC-2 functions such as line coding, CRC check / calculation, primitive generation / decoding and credit based flow control. The Core also includes FIFOs and an Atlantic interface to simplify system design and integration of third party Cores. The transport Core interfaces industry standard SERDES devices with a 10-Bit or a 20-Bit interface. For higher integration, the Transport Core can be implemented in Altera StratixGX devices eliminating the need of an external SERDES device.

The Fibre Channel Transport Core is optionally available with an Avalon interface that provides connectivity to an Altera NIOS processor and a large selection of peripherals (e.g. UARTs, Timers, Memory Interfaces) and Cores (e.g. Ethernet MAC, POS-PHY interfaces, PCI, PCI-X). For ease of use, the Fibre Channel Core is integrated in Altera SOPC Builder easing system generation.