Altera and Micron Announce Industry’s First DDR400 SDRAM DIMM Interface for FPGAs

“Micron understands the importance of enabling customers with various tools and resources for high-speed system designs taking advantage of emerging memory technologies,” said Deb Matus, Micron’s product marketing manager for networking and communications.   “We are focusing not only on developing advanced memory technology, but also on ways to help our customers implement our new high-performance memory products.  Rigorous testing was performed on the interface of our DDR SDRAM-based DIMMs with Altera’s Stratix and Stratix GX devices.  The Altera devices achieved the maximum desired performance of 400 Mbps in each of these operating scenarios, demonstrating their ability to deliver the robust memory interfaces demanded by today’s high-end systems.”

FPGAs are increasingly used to interface with DDR SDRAMs in a wide variety of applications.  Designers often face a number of challenges in building memory interfaces because of the requirement to shift the DQS signal by 90 degrees during the read operation.  The built-in DQS phase shift circuitry found only in Altera’s industry-leading FPGAs is the optimal phase shift solution and eliminates the need to use less efficient design techniques such as varying signal trace lengths or adding fixed delay elements, which dramatically complicate board design.

The easy-to-use DQS phase shift circuitry in Stratix and Stratix GX devices automatically shifts the DQS signal 90 degrees, simplifying design.  In addition to the DQS phase shift feature, Stratix and Stratix GX devices support advanced features that are essential for building reliable, high-speed memory interfaces, including:  six registers in the I/O element for high-speed DDR signaling, SSTL I/O standard support for interfacing with DDR SDRAMs, feature-rich PLLs for efficient clock management, and a robust clock distribution network for minimizing skew between clock and data channels.  “DDR SDRAM memory interface designs, especially those using DIMM interfaces, are challenging to implement,” said David Greenfield, senior director of product marketing for FPGA products at Altera.  “The built-in DQS phase shift circuitry in Stratix and Stratix GX devices dramatically simplifies this design process.”

Altera’s Stratix and Stratix GX DDR SDRAM interfaces are hardware-verified to operate at 400 Mbps with DIMMs under worst-case conditions.  This ensures customers have a low-risk path to DDR SDRAM interface implementation.  In addition, customers can now evaluate Stratix and Stratix GX device-based DDR SDRAM interfaces at 400 Mbps using two DDR demo boards:  the PCI Development Kit, Stratix Edition, which comes with a DDR400 SODIMM interface, and the Stratix GX Development Kit, which comes with a DDR400 DIMM.  Both the kits come with the evaluation version of Altera’s DDR SDRAM controller IP for accelerating memory interface design cycles.   

Altera’s DDR SDRAM controller IP was verified using the commonly used Denali Memory Models—Advance Verification (MMAV).  Altera provides its customers an evaluation version of Denali’s MMAV models free of charge. “Altera’s high-performance DDR memory controller requires bug-free, accurate models to extract the most performance in the shortest time to market,” said Mark Gogolewski, CTO of Denali Software.  “Denali’s Memory Modeler Advance Verification (MMAV) has proven itself in a wide variety of design flows as an effective tool for helping ASIC designers rapidly and accurately verify that their circuits achieve the highest performance with external memories like Micron’s 400-Mbps DDR SDRAM.   We are pleased to offer MMAV to Altera’s customers.”

Altera also provides a complete system solution, including extensive technical documentation, characterization reports, software and tool support, SPICE and IBIS simulation models, development boards and intellectual property (IP) cores, to help system designers successfully interface Altera FPGAs to DDR SDRAMs.  More information can be found at www.altera.com/products/devices/stratix/features/stx-ddr_sdram.html. In addition, the results, test set-up and design file information used in verifying interoperability between Micron’s DDR SDRAMs and Altera’s Stratix devices are available at www.altera.com/products/devices/stratix/features/stx-interface.html. For more information about Altera’s Stratix and Stratix GX FPGAs visit the Altera web site at www.altera.com.