Silicore Releases VMEbus to PCI Bridge System-on-Chip (SoC) Under Open Source License
January 20, 2004 - Bus & Board Conference / Long Beach, CA - USA. Silicore Corporation announced today the release of a VMEbus to PCI Bridge System-on-Chip under open source licensing. The bridge system is provided as a VHDL soft core, and is intended to run on Field Programmable Gate Array (FPGA) chips.
The bridge SoC is released under the GNU Lesser GPL License (LGPL). Under that license anybody can download, use and modify the bridge code without any royalties or other fees. According to Wade Peterson, President of Silicore, "This bridging system uses a dual, internal WISHBONE System-on-Chip bus. They are organized as 16-slot backplanes with shared memory blocks. The memory blocks can be replaced with other off-the-shelf core functions, such as those available from the OpenCores organization. This is a very nice, modular structure where the System-on-Chip acts like a modular VMEbus system."
In a related move, Silicore also announced its support for a new initiative called OpenVME. This is a community development program aimed at creating and promoting VMEbus interface IP. Peterson added that: "We think this strategy will foster development of whole new interface technologies. This will be done through community code development much like we see in the GNU/Linux world. In order to get things rolling, Silicore is releasing this bridge system under the LGPL license. This thing could serve as 'seed code' for the development of other interfaces."
-
Download a copy of the Bus and Board Conference presentation (Adobe Acrobat® 5.0 '.PDF' file, 147 Kb)
Contact Information and Related links:
- Silicore Corporation website: www.silicore.net
- Download the bridge System-on-Chip at: www.silicore.net/vmecore.htm
- OpenCores website: www.opencores.org
- The Bus and Board Conference: www.busandboard.com
Press release copyright (C) 2004 Silicore Corporation. Verbatim copying and distribution of this press release in any medium is permitted, provided this notice is preserved.
|
Related News
- Synopsys Releases Proven VMM Methodology Standard Library and Applications Under Apache Open Source License
- Silicore Adopts Open Source Business Model for Semiconductor IP; Releases SLC1657 uP Core Under LPGL
- Parthus and 1st Silicon License Agreement Provides New Foundry Source for System-on-Chip IP
- Saankhya Labs receives approval under Semiconductor Design Linked Incentive (DLI) scheme for Development of a System-on-Chip (SoC) for 5G Telecom infrastructure equipment
- Renesas Electronics Receives USB-IF Certification for its USB 3.0-SATA3 Bridge System-on-Chip
Breaking News
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- Keysom Unveils Keysom Core Explorer V1.0
Most Popular
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- Ceva, Inc. Announces First Quarter 2025 Financial Results
- Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |