Platforms key to cost reduction: Rhines

Wally Rhines, speaking at an event here, said the industry is splitting into two distinct groups, those that create design platforms and those that use them to design systems.

"What's really needed is an entire design platform where you have available to you embedded microprocessors, digital signal processors, standard busses, tightly coupled peripherals, loosely couple peripherals," he said. "And what you'd like as a system designer is to be able to plug and play with those components without all the detail without having to design each gate individually. In fact that exists today. It's not widely used."

Rhines, in framing Moore's Law as an empirical observation rather than a law, noted that baseline estimates for designing an ASIC today start at $20 million, far too expensive a development cost for most markets.

Structured ASICs, in which a handful of masked layers are left open to programmability late in the design process, are still struggling for acceptance. Some companies have moved to a higher level of abstraction, releasing designs at the register transfer level (RTL) stage or compiling straight from C and C++, he noted.

"Ultimately we will have to address a change in ASIC metholdogy," he said. "It's really only with a (platform-based) method like this that we can go from that $20 million down to $2 million or $3 million that enable an ASIC design world that can attack lower volume applications," Rhines said.

Pounding away at other segments of the industry, Rhines noted that both lithography and test costs are soaring. Lithography machines now cost tens of millions of dollars, and while the manufacturing cost per transistor has decreased over time, the test cost per transistor has not.

"This cannot continue indefinitely," he said. The EDA industry has responded to a degree by offering relatively new design-for-manufacturing and design-for-yield tools to help address some of these problems, he noted.