Dolphin's Read-Only Memory generator embeds the highest density on standard CMOS

September 1, 2004 -- Dolphin Integration has released its CASSIOPEIA-HSL architecture for the tROMet-LP in both 0.18 µm and 0.13 µm logic CMOS.

Its aggressive ultra-high density and low-power trade-off is a must for portable devices and it already prevails in wireless equipment such as Bluetooth modules.

Expected area savings over usual metal ROMs: 2 mm² in 0.18 µm and 1 mm² in 0.13 µm process for an instance of 4 Mbit.

Under worst-case conditions for dynamic power consumption, an 8 Mbit tROMet instance in TSMC 0.18 µm consumes only 170 µA/MHz, for an area of 5.048 mm².

Flip-tROMet-LP-0.18µm-CASSIOPEIA-HSL - generates instances at will from 1 Mbit up to 8 Mbit thanks to its three-layer programming patent and features:

• 2-bit patented bit-cell for featuring high-density
• Auto sequencing for top yield together with data signal matching
• The smart architecture enhancing command signal simplicity
• A breakthrough in both high-speed and low-power.

Figure-out your preferred instance on-line by Front-End Generation for FREE at:
http://www.dolphin.fr/flip/ragtime/ragtime_overview.html

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