D&R Headline News | Most Popular | SoC News Alerts | |

Commentary / Analysis

• Growth of Integrated Circuits in 2005 Was 7.8%, 2006 Expected to Be in Double-Digits (Thursday Feb. 02, 2006)
  Revenues and unit sales of worldwide Integrated Circuits (ICs) in 2005 grew 7.8% and 10.6%, respectively, and 2006 is expected to be even more robust, claims Advanced Forecasting, a semiconductor-oriented forecasting house
  
  
• Leakage takes priority at 65 nm (Monday Jan. 16, 2006)
  As the first reports on 65-nanometer design come in from the field, the good news is that there don't appear to be any problems at 65 nm that weren't there are 90. The bad news is that some of the problems that plagued 90 nm get much worse at the new node
  
  
• Are DSPs disappearing? (Monday Jan. 16, 2006)
  Looking at the past year, a striking trend emerges: Increasingly, the hardware used for signal processing is something other than a DSP.
  
  
• Design outsourcing: navigating a maze of decisions (Monday Jan. 09, 2006)
  The cheapest, fastest and best way to finish your chip design may be to get somebody else to do it. A complex web of providers, both domestic and offshore, will be happy to help.
  
  
• Maintaining Low Power Consumption on Chips is Critical to Drive Wireless Internet on a Chip Technology (Tuesday Jan. 03, 2006)
  The challenge for wireless device manufacturers lies in developing handheld devices that offer an array of services while maintaining power-efficiency and offering high-performance
  
  
• On-chip nets look to rewire next-gen ICs (Monday Dec. 26, 2005)
  Silistix Ltd. and STMicroelectronics have come up with very different approaches to a widespread problem: how to keep the fixed buses that link today's systems-on-chip from running out of steam
  
  
• Video architectures vie for mainstream (Monday Dec. 19, 2005)
  Digital video processing is rapidly becoming the premier signal-processing challenge
  
  
• Memories look to new materials set (Monday Dec. 19, 2005)
  Now, memories are set to undergo an equally dramatic series of materials and design changes, ranging from new dielectrics in DRAM and flash to SRAMs with eight transistors per cell, said participants at the recent International Electron Devices Meeting in
  
  
• SoC value linked to software (Monday Dec. 12, 2005)
  Chip designers can no longer live by silicon alone, said analysts at last week's Gartner Dataquest semiconductor industry briefing here
  
  
• Love-hate relationship: EEs and IP (Monday Dec. 12, 2005)
  There's an inherent contradiction in how engineers think about intellectual property. On the one hand, they seek out IP, expecting it to reduce their design time, resource requirements and risk. On the other hand, they believe that adopting external IP wi
  
  
• External IP: Who are decision makers? (Monday Dec. 12, 2005)
  The first question to ask in examining how design teams select intellectual property is who does the selecting
  
  
• Quality, easy integration are on IP 'must have' list (Monday Dec. 12, 2005)
  Some of the key areas where we see IP selection trends evolving over the next two to three years are in IP quality evaluation, ease of IP integration, performance validation, signaling of vendor maturity and the ability to easily reconfigure IP
  
  
• TSMC exec sees more IP from foundry (Thursday Dec. 08, 2005)
  Taiwan Semiconductor Manufacturing Co. Ltd.'s Europe technical director said the giant foundry's venture into library design was only the beginning of an increasing presence in the IP industry
  
  
• Fabless Business Model Not Working, Say CEOs (Thursday Dec. 08, 2005)
  The fabless semiconductor business model is dysfunctional, and can only be got to work again if there are some significant technical breakthroughs, according to a number of company chief executives.
  
  
• Unlocking the IP vault (Thursday Dec. 01, 2005)
  Startup retools in-house chip technology for the mass market
  
  
• Back to the drawing board (Monday Nov. 28, 2005)
  You've probably been hearing a lot of buzz about multiprocessor chips. Putting multiple processors on a chip isn't a new idea. But such chips are gaining momentum both in general-purpose computing applications and in embedded systems.
  
  
• Court broadens IP protections (Monday Nov. 21, 2005)
  A Silicon Valley dispute festering in the courts since 1999 will likely have far-reaching impact on how chip designers protect their intellectual property
  
  
• ARCHITECTURES: MCUs bulk up for tasks once handled by ASSPs (Monday Nov. 21, 2005)
  With a careful choice of peripherals and an eye toward an inexpensive companion chip - or perhaps a small FPGA or structured ASIC to meet specific peripheral needs - a standard-product microcontroller can be turned into a formidable applications engine
  
  
• Devices must function despite defects, says panel (Tuesday Nov. 08, 2005)
  Major changes to design philosophy are need at sub-90-nanometer nodes to accommodate the shrinking number of atoms on each transistor, according to a Monday evening (Nov. 7) panel discussion at the International Conference on Computer Aided Design here
  
  
• Making life easier for multicore SoC software developers (Monday Nov. 07, 2005)
  Putting multiple processors on a single chip or on a single board has enabled embedded system hardware designers to provide more features and higher processing speeds using less power, thus solving many design problems. But for software developers - and v
  
  
• Tools help harness multicore power (Monday Nov. 07, 2005)
  While the benefits of multiple cores have been well-documented, the programming tools have not-until now
  
  
• Panel studies power in SoCs (Friday Nov. 04, 2005)
  A panel discussion at the 3rd International System-on-Chip Conference here this week attempted to skip past the academic science projects and the rosy vendor marketing and explore what was really feasible today in the challenging area of power management
  
  
• Programmable logic outpacing MPU industry, Altera exec claims (Thursday Nov. 03, 2005)
  
  
  
• Electronic Design Survey Shows 73 Percent of mainland China and Taiwan Engineers Design Asics Using 0.18-Micron Technology - up 21 Percentage Points From 2004 (Thursday Nov. 03, 2005)
  Mainland China & Taiwan, shows that 73 percent of mainland China and Taiwan engineers are using 0.18 micron or finer process technology in application-specific integrated circuit (ASIC) design -- up 21 percentage points from 2004
  
  
• Software limits multi-core ICs, panelists say (Wednesday Oct. 26, 2005)
  Multi-core ICs promise efficiency and performance, but will require new programming models that hide software and hardware details, according to panelists at the GSPx 2005 conference here Tuesday (Oct. 25)
  
  
• Go with the EDA flow, says SPIRIT (Tuesday Oct. 25, 2005)
  The SPIRIT Consortium is a global organisation concerned with supply-chain collaboration looking to provide a practical answer to multi-vendor design-flow integration, says vice-chairman Christopher Lennard
  
  
• Supercores won't be easy to fabricate (Monday Oct. 17, 2005)
  ARM Ltd. raised few eyebrows with the long-anticipated announcement of its Cortex A8 CPU core a couple of weeks ago. But the launch did raise two important questions: Who really needs a 1-GHz general-purpose CPU core, and if it is needed, who will be capa
  
  
• Best practices for structured-ASIC design (Monday Oct. 17, 2005)
  Given the increasing nonrecurring engineering charges and long design schedules associated with deep-submicron standard-cell ASICs, the use of structured ASICs for custom IC design is an increasingly attractive option
  
  
• C link remains frayed in hardware design flows (Monday Oct. 17, 2005)
  C models are not fully integrated into a system-level flow; instead, they serve as point tools for exploring algorithms and partitioning before the real hardware design begins
  
  
• When it comes to IP, caveat emptor, panel says (Friday Oct. 14, 2005)
  Intellectual property buyers must be forewarned and forearmed before they dive into purchasing IP cores, a panel of industry experts insisted Thursday (Oct. 13).