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IP / SOC Products News

• MoSys Demonstrates Blu-Ray Solution for Home Entertainment Applications (Tuesday Jul. 01, 2008)
  The MoSys solution is the first in the industry to support all next-generation Blue-Laser and current Red-Laser DVD formats in a single, integrated design for multi-format DVD players and recorders, game consoles, PCs, advanced Set-Top boxes, and digital video recorders.
  
  
• Lattice Enhances its Wireless Base Station Solutions Portfolio (Monday Jun. 23, 2008)
  Lattice Semiconductor Corporation today announced the availability of three new Intellectual Property (IP) core and reference design products targeting the wireless communications market.
  
  
• Kaben Wireless Silicon releases high-performance frequency synthesizer for WiMAX applications (Tuesday Jun. 17, 2008)
  The Fractional-N synthesizer delivers a -116 dBc/Hz phase noise performance and -90 dBc spurious response at 6 GHz output
  
  
• IP Cores, Inc. Shipped Ultracompact AES and AES/GCM IP Cores for Actel FPGA Supporting FIPS-197, IEEE 802.1AE MACsec and P1619.1 Standards (Monday Jun. 16, 2008)
  Starting at 800 tiles for AES1-8E and delivering 11.2 Mbps on RTSX radiation-tolerant devices, AES and AES/GCM cores provide a compact and high-performance solution for an FPGA designer working on a secure communication solution.
  
  
• Virage Logic Unveils One Mega-Bit Embedded Reprogrammable Non-Volatile Memory (NVM) on Standard CMOS Process (Monday Jun. 16, 2008)
  Combining user-defined functionality with Virage Logic’s high-capacity read-only memory (ROM) and NOVeA® Flash memory, emPROM provides secure, fully integrated embedded NVM for SoC designs requiring up to 16 Megabits of code storage and is manufactured on industry standard CMOS processes with no additional mask or process steps.
  
  
• Radiocomp & Altera partner on OBSAI/CPRI cores (Thursday Jun. 12, 2008)
  Denmark-based Radiocomp and Altera Corporation today announced an integrated, rapid development solution for developers of WiMAX and 3GPP LTE base station equipment.
  
  
• Faraday Announces the First Commercially Available 1GHz Memory Compiler to Enable GHz CPU & SoC Designs in UMC 90nm (Thursday Jun. 12, 2008)
  The single-port memory compiler utilizes advanced layout and circuit design techniques to provide up to 1GHz speed and keeps the same power and area requirement as generic memory solutions.
  
  
• austriamicrosystems further expands field-programmable OTP memory portfolio for its advanced 0.35um process family (Thursday Jun. 12, 2008)
  The polyfuse-based OTP memory cell “PPROM” is available in two fixed sizes of 4x8 bit and 16x8 bit and comes with a parallel interface. It is accessible like a static RAM and offers direct addressed outputs. The “PPTRIM” blocks available in sizes of 8 bit, 16 bit, 32 bit, 48 bit and 64 bit offers a three wire interface and auto-load at poweron reset.
  
  
• Synopsys Announces DesignWare IP for PCI Express with PCI-SIG I/O Virtualization Technology (Wednesday Jun. 11, 2008)
  The PCI-SIG I/O Virtualization (IOV) technology, which builds on the PCI Express (PCIe) protocol stack, reduces the system hardware requirements by enabling the simultaneous sharing of peripherals across multiple CPUs or operating systems.
  
  
• Tiempo announces a fully-asynchronous delay insensitive DES crypto-processor chip (Wednesday Jun. 11, 2008)
  Tiempo released a clock-less crypto-processor chip - DES4- including four different DES cores available as IP and able to execute standard ciphering algorithms DES, DES-1, 3DES & 3DES-1.
  
  
• GDA Demonstrates its PCI-Express Gen 2 Controller (GPEX-GEN2) at 5Gbps for High Performance Applications (Wednesday Jun. 11, 2008)
  GDA Technologies today announced successful functional operation of its Gen2 PCI Express Controller on its hardware platform.
  
  
• Lattice Expands Wireless Solutions with 3GPP-LTE CTC Decoder IP Core (Monday Jun. 09, 2008)
  TurboConcept Optimizes its 3GPP-LTE Turbo Decoder IP Core for LatticeSC/M and LatticeECP2/M FPGA Devices
  
  
• IPextreme® Brings ColdFire® Architecture to the FPGA Masses (Monday Jun. 09, 2008)
  IPextreme today announced an FPGA-optimized soft version of Freescale’s V1 ColdFire® core available free of charge to Altera’s Cyclone III FPGA customers
  
  
• Freescale and Altera Partner to Deliver World's First Soft ColdFire(R) Cores on FPGAs (Monday Jun. 09, 2008)
  Popular V1 Core Available at No Charge Through IPextreme for Altera's Cyclone(R) III FPGA; SOPC Builder-Ready Component Backed by Broad Ecosystem
  
  
• Dolphin Integration launches their SESAME library for High Voltage and Low Leakage in 0.18 µm (Monday Jun. 09, 2008)
  Direct connection to the battery (e.g. Li-Ion) for some logic islets of SoCs requires dealing with “high voltage”, up to 3.6 V, while for others ultra low leakage is needed far below the performances offered by products available on the market.
  
  
• Noesis Technologies releases 10Gbps AWGN channel emulator IP (Friday Jun. 06, 2008)
  The core is fully programmable, able to support throughput rates up to 10Gbps, rendering it an ideal solution for channel emulation of high data rate applications such as GPON, G.975 and others.
  
  
• Innovaide Releases Licensable Packet Processing and Traffic Management IP (Thursday Jun. 05, 2008)
  Innovaide is First-to-Market with licensable Carrier Grade designs for Classification, Forwarding and Traffic Management. The Verilog blocks scale from 5Gig to 40Gig performance in FPGA/ASIC implementations.
  
  
• Arasan Chip Systems PCI Express Gen2 Solution Named to PCI-SIG Integrators List (Thursday Jun. 05, 2008)
  New Flexible PCIe IP Core and Development Platform Passes Rigorous Interoperability and Compliance Testing
  
  
• Evatronix enhances its Ethernet MAC product line with MAC-1G PCS IP core (Thursday Jun. 05, 2008)
  Physical Coding Sublayer (PCS) add-on to the successful MAC-1G controller provides new opportunities for an already wide range of possible implementations.
  
  
• Imagination Technologies Extends Low-Power Receiver IP Platform (Thursday Jun. 05, 2008)
  Imagination Technologies announced today that it has added NorDig-Unified 1.0.3.compliant DVB-T to its licensable receiver IP platform family.
  
  
• Virage Logic Supports TSMC's Power Trim Service(TM) for Advanced Process Nodes (Tuesday Jun. 03, 2008)
  With its advanced tradeoff capabilities, SiWare Memory users can achieve static power savings of up to 35 percent, 70 percent or 90 percent depending on their selection of the built-in light sleep, deep sleep and shut-down modes available in 40nm memories.
  
  
• Virage Logic Delivers Open RTL to Test Floor Embedded Memory Test and Repair Subsystem (Monday Jun. 02, 2008)
  New Release of STAR Memory System Expands Availability of Subsystem Beyond Virage Logic Memories to Third-Party and Internally Developed Memories
  
  
• ARM Mali-400 MP Technology Brings High-end Graphics to all Consumer Devices (Monday Jun. 02, 2008)
  ARM today announced the ARM® Mali™-400 MP scalable multiprocessor graphics solution, capable of delivering performance of up to 1G pixels per second and enabling licensees to serve multiple product markets with the same architecture, whilst retaining the flexibility to choose the optimum power, performance and area configuration for their application.
  
  
• Xilinx Meets Performance Requirements of LTE Wireless Systems With New LogiCORE Turbo Encoder and Decoder Solutions (Friday May. 30, 2008)
  The new Xilinx 3GPP LTE Turbo Encoder and Decoder LogiCORE(TM) offerings deliver throughput speeds of up to 200 Mbps with the embedded digital signal processing (DSP) capabilities of Spartan(R) and Virtex(R) field programmable gate arrays (FPGAs)
  
  
• Denali First to Release Full DDR3 DIMM IP Solution (Thursday May. 29, 2008)
  This new DDR3 DIMM offering adds unique capabilities in the memory controller and PHY IP that are needed for networking, storage and personal computing systems using DDR3 modules at data rates up to 12.8GBytes/s per DIMM.
  
  
• DapTechnology announces VHDL Testbench for its FireLink Extended 1394b link layer controller IP Core (Wednesday May. 28, 2008)
  The FireLink Extended Testbench is transaction based and allows verification level and diagnostic tests to be performed from a system level perspective.
  
  
• Virage Logic Speeds Time-to-Market with an All-Digital, High-Performance DDR2/3 PHY+DLL Solution (Wednesday May. 28, 2008)
  Supporting speeds of up to 1066 Mbps in 65-nanometer (nm) G processes, the all-digital Intelli DDR2/3 PHY+DLL achieves performance and resolution levels that were previously only possible with analog solutions.
  
  
• MIPS Technologies Unveils Silicon-Proven Hi-Fi Audio Playback IP With Lowest Power Consumption Available (Tuesday May. 20, 2008)
  The new Audio Codec IP achieves an impressive 100dB dynamic range and -93dB THD while consuming only 7.8mW power when playing back through stereo line outputs at 48kHz.
  
  
• Algotronix launches unique DesignTag system for detecting proprietary intellectual property within an operating chip (Monday May. 19, 2008)
  DesignTag consists of a small, low power, IP core which is added to the design to be protected and DesignTag reader software and data logging hardware which can sense the tag through the chip package. Each DesignTag IP core has a unique identification code which can be used to look up details of the protected product in a database.
  
  
• Evatronix announces its fifth 8051 ISA-based SoC Development Platform - HDLC Connectivity. (Monday May. 19, 2008)
  HDLC controller joins other IP cores in the R8051XC-based platform family, Ethernet MAC and USB Controllers, to shorten time-to-market for data communication solutions