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IP / SOC Products News

• LeapMind Announces the Beta Release of their Ultra-low Power Consumption AI Inference Accelerator IP (Tuesday Oct. 05, 2021)
  LeapMind Inc., a creator of the standard in edge AI (Shibuya-ku, Tokyo; CEO: Soichi Matsuda) today announced the beta release of ultra-low power consumption AI inference accelerator IP “Efficiera” version 2 (v2) before its commercial launch by the end of this year.
  
  
• Weebit demonstrates successful scaling of its ReRAM technology to 28nm (Monday Oct. 04, 2021)
  Weebit Nano, a leading developer of next-generation memory technologies for the global semiconductor industry, together with its development partner CEA-Leti, have demonstrated production-level parameters of Weebit’s Resistive Random-Access Memory (ReRAM) technology in a 28 nanometre (nm) process.
  
  
• Arasan announces its Total MIPI Soundwire IP Solution with the launch of its Soundwire PHY IP (Friday Oct. 01, 2021)
  Arasan Chip Systems, a leading provider of semiconductor IP for the IoT), mobile and automobile SoC's announces the immediate availability of its MIPI Soundwire PHY I/O IP. With this IP, Arasan now provides a Total IP solution for MIPI Soundwire in compliance with the latest Soundwire Specifications v1.2
  
  
• SoC-e Announces 10G Multiport TSN Switch Release (Wednesday Sep. 29, 2021)
  The new 10G MTSN Switch IP Core uses a totally redesigned switching architecture that has been designed with higher speeds in mind (used also in our 10G Managed Ethernet Switch), while still being compatible with legacy speed ports.
  
  
• Fraunhofer IPMS presents a scalable TSN multiport switch at the TSN/A conference (Wednesday Sep. 29, 2021)
  Fraunhofer IPMS develops platform-independent TSN IP cores for FPGA and ASIC implementations and offers development services for customer-specific system developments based on them. The latest development is a multiport TSN switch IP core. In its standard configuration, the core provides four external ports and one internal CPU port. However, the flexible design of the core allows scaling up to 16 ports.
  
  
• Bluespec, Inc. Releases Ultra-Low Footprint RISC-V Processor Family for Xilinx FPGAs, Offers Free Quick-Start Evaluation. (Tuesday Sep. 28, 2021)
  Bluespec, Inc., a founding member of RISC-V International and supplier of RISC-V Processor IP and tools, released the MCU RISC-V processor family targeted at ultra-low resource utilization on Xilinx FPGAs
  
  
• Intrinsic ID Announces NIST-Certified Software Random Number Generator (Zign RNG) for IoT Devices (Tuesday Sep. 28, 2021)
  Intrinsic ID today announced Zign RNG, a new offering enabling IoT chip providers and device makers to establish a high-security random number generator in software enabling it to be deployed on devices even after silicon fabrication to ensure a true source of randomness for IoT devices.
  
  
• intoPIX extends its range of TICO-RAW IP-cores with smaller architectures supporting a wider range of image sensors and cameras (Tuesday Sep. 28, 2021)
  intoPIX, the leading provider of innovative compression solutions, announces today the extension of its range of TICO RAW IP-cores supporting additional pixel per clock architectures to target more devices and more sensor types.
  
  
• Allegro DVT and Beamr Announce the World's First Content-Adaptive Silicon IP Video Encoder (Thursday Sep. 23, 2021)
  Allegro DVT, the leading provider of video processing silicon IPs, and Beamr, the leading developer of content-adaptive video encoding technologies, today announced an integrated solution that combines Beamr’s CABR silicon IP with Allegro’s video encoding IP to create the world’s first content-adaptive silicon IP encoder.
  
  
• Xiphera expands its Advanced Encryption Standard portfolio (Thursday Sep. 23, 2021)
  Xiphera extends its AES portfolio by launching XIP1123B, a balanced versatile IP core supporting AES with 256-bit key length in five modes of operations (ECB, CBC, OFB, CFB, and CTR). XIP1123B is primarily targeted for linerates of a few Gbps, and the mode of operation can be dynamically changed by the user.
  
  
• EPI EPAC1.0 RISC-V Test Chip Samples Delivered (Wednesday Sep. 22, 2021)
  The European Processor Initiative (EPI) is proud to announce that EPAC1.0 RISC-V Test Chip samples were delivered to EPI and initial tests of their operation were successful.
  
  
• DCD-SEMI introduces octa SPI IP Core for smart wear, audio and mobile (Tuesday Sep. 21, 2021)
  Drive for richer graphics, higher data throughput and wider range of multimedia forces engineers to enable more sophisticated features in embedded applications. But the higher data throughputs require extra demands on the often-limited MCU on-chip memory. That’s why DCD-SEMI mastered DOSPI – octa SPI, to enhance the line of dual and quad SPI IP Cores.
  
  
• 100G MAC and 100G PCS IP Cores for high performance applications are now available (Tuesday Sep. 21, 2021)
  Comcores ApS, a fast-growing specialized supplier of Intellectual Property (IP) Cores, today announced the availability of a 100G Ethernet MAC IP including the Reconciliation Sublayer (RS), as well as a 100G PCS IP that includes RS-FEC and Base-R (SC)- FEC sublayers.
  
  
• Synopsys Advances Processor IP Leadership with New ARC DSP IP Solutions for Low-Power Embedded SoCs (Monday Sep. 20, 2021)
  To address the broader range of power, performance and area (PPA) demands of embedded applications, Synopsys, Inc.today announced it has expanded its DesignWare® ARC® Processor IP portfolio with new 128-bit ARC VPX2 and 256-bit ARC VPX3 DSP Processors.
  
  
• Xiphera launches solutions for encrypted data storage (Friday Sep. 17, 2021)
  To address the needs to secure data at rest, Xiphera has expanded its product portfolio by adding two Intellectual Property (IP) cores to its offering. The freshly added IP cores are based on the AES-XTS, which is the most popular standard for encrypting data on block-oriented storage devices and formally defined in IEEE Standard 1619-2018.
  
  
• intoPIX Releases a New Range of Compact Encoders and Decoders for JPEG XS (Thursday Sep. 16, 2021)
  intoPIX, the leading provider of innovative compression solutions, announces today the release of new extra small JPEG XS IP-cores for FPGA and ASIC.
  
  
• Mixel Announces Immediate Availability of MIPI C-PHY/D-PHY Combo IP on TSMC N5 Process (Tuesday Sep. 14, 2021)
  Mixel®, a leading provider of mixed-signal intellectual property (IP), announced today that its MIPI® C-PHYSM/D-PHYSM Combo IP is now available on TSMC’s industry-leading N5 process. The MIPI C-PHY IP supports the v2.0 specification, and the MIPI D-PHY IP supports the MIPI D-PHY v2.5 specification.
  
  
• SmartDV Provides Broad Portfolio of Memory Modeling, Design and Verification Solutions (Tuesday Sep. 14, 2021)
  The SmartDV portfolio provides memory controller Design IP for all derivatives of DDR, LPDDR and Flash and supports the DDR PHY Interface (DFI) specification. Memory models and Verification IP are available for DDR, GDDR, ONFI, TCAM, FLASH, HBM, non-volatile memories and DIMM, and others.
  
  
• MIPI UFS v3.1 Ctrl., MIPI UniPro v1.8 Ctrl. & MIPI M-PHY v4.1 IP Cores in 12nm & 28nm available for immediate licensing for high performance serial interface applications (Monday Sep. 13, 2021)
  T2MIP is pleased to announce the immediate availability of its’ partners MIPI UFS v3.1 Controller IP Core, MIPI UniPro v1.8 Controller IP Core and MIPI M-PHY v4.1 IP Core silicon proven 12nm FinFET Compact (FFC) and 28nm High-Performance Computing Plus (HPC+) semiconductor processes. T
  
  
• Cadence Accelerates Intelligent SoC Development with Comprehensive On-Device Tensilica AI Platform (Monday Sep. 13, 2021)
  Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its Tensilica® AI Platform for accelerating AI SoC development, including three supporting product families optimized for varying data and on-device AI requirements.
  
  
• eMemory's Security-Enhanced OTP IP Qualified on TSMC N6 Process (Thursday Sep. 09, 2021)
  eMemory, the world’s leading provider of semiconductor intellectual property (IP), today announces the security-enhanced version of its One Time Programmable (OTP) IP, NeoFuse, has been qualified on TSMC’s N6 process.
  
  
• System Level Solutions's eUSB 3.1 Gen2 Device Controller (eUSB31SF) IP core now available with Isochronous transfer support (Thursday Sep. 09, 2021)
  For 16 years, SLS has been providing USB IP core solutions. After many successful deliveries for various high-speed data transfer applications, SLS has now launched an eUSB 3.1 Gen2 Device Controller (eUSB31SF) IP core with Isochronous transfer type support.
  
  
• QuickLogic Announces Australis eFPGA IP Generator (Wednesday Sep. 08, 2021)
  Continuing QuickLogic's commercial leadership in open-source tools, Australis is based on the OpenFPGA IP generator and adds a multitude of additional features and capabilities specific to implementing QuickLogic's eFPGA IP solutions, along with the level of testing and support required to build commercially viable eFPGA IP.
  
  
• Sondrel's IP platform provides powerful computing at the Edge with integrated Arm security subsystem (Tuesday Sep. 07, 2021)
  The resulting, single channel ASICs can be arrayed together to form scalable processing solutions and additional features can be added in a modular fashion. Applications include smart metering, smart homes, smart factories, voice-controlled devices and infotainment.
  
  
• Quantum-driven semiconductor IP for IoT security verified as PSA Certified Level 2 Ready (Monday Sep. 06, 2021)
  Crypto Quantique, a specialist in quantum-driven cybersecurity for the internet of things (IoT), has received confirmation from independent security experts, Riscure, that its QDID quantum-driven semiconductor IP is PSA Certified Level 2 Ready.
  
  
• sureCore announces development of cryo-CMOS IP that will unlock Quantum Computing's potential (Wednesday Sep. 01, 2021)
  sureCore, the ultra-low power embedded IP specialist, has announced that it is developing a range of CMOS IP suitable for operation at the extremely low temperature required for Quantum Computing (QC) applications.
  
  
• GUC Announces Industry Highest Bandwidth and Power Efficient Die-to-Die (GLink 2.0) Total Solution (Tuesday Aug. 31, 2021)
  Global Unichip Corp. (GUC) disclosed today that its 2nd generation GLink 2.0 (GUC multi-die interLink) interface, using TSMC 5nm process and TSMC advanced packaging technology for multi-die integration in AI, HPC and Networking applications, has passed full silicon qualification.
  
  
• Rambus Demonstrates Industry-first PCIe 5.0 Digital Controller IP for FPGAs (Tuesday Aug. 31, 2021)
  Rambus today announced that Rambus has demonstrated its PCI Express® (PCIe) 5.0 digital controller IP on leading FPGA platforms.
  
  
• Arasan Chip Systems announces its 2'nd Generation Sureboot QSPI IP (Wednesday Aug. 18, 2021)
  Arasan Chip Systems announces the immediate availability of their formally verified Sureboot™ QSPI IP. The Silicon Proven QSPI NOR Flash memory controller IP is an extended version of the SPI protocol allowing the use of 4 data lanes leading to highly effective overall bandwidth.
  
  
• Hirose and eTopus Technology Develop Combined 112Gbps Interconnect Solution for AI Training Applications (Wednesday Aug. 18, 2021)
  Hirose Electric Co., Ltd., a global leader in connector technology, its design, and manufacturing, and eTopus Technology, a pioneer of ultra-high-speed ADC/DSP-based SerDes for wireline applications including data center, cloud, edge, and 5G base stations, today announced the development of a 112Gbps interconnect technology built on their products.