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IP / SOC Products News

• Cobham Releases RISC-V Processor IP Core (Wednesday Dec. 11, 2019)
  Cobham Gaisler announced today that it will release a new line of processor Intellectual Property (IP) cores that implements the RISC-V instruction set architecture (ISA). The NOEL-V processor IP core, the first product in the family, will be made available on 25 December for download into Xilinx’ Kintex UltraSCALE FPGAs.
  
  
• Cobham Releases LEON5 Processor IP Core (Wednesday Dec. 11, 2019)
  The new LEON5 IP core implements the SPARC V8 32-bit ISA, a 32-bit architecture. LEON5 is a super-scalar dual-issue processor that provides software backward compatibility with previous generation LEON processors while increasing performance both in terms of maximum achievable operating frequency and amount of computations performed per system clock cycle.
  
  
• AccelerComm Reduces 5G Latency by up to 16x with NR LDPC Channel Coding (Wednesday Dec. 11, 2019)
  AccelerComm announced today the launch and general availability of the 5G NR LDPC version of its error correction IP, which reduces latency up to 16x to support numerology 4 in 3GPP 38.211 and also results in significant power savings for mobile networks with lower order numerology networks.
  
  
• SiFive Announces New Technologies for Mission-Critical and AI Markets (Wednesday Dec. 11, 2019)
  New SiFive Apex cores for mission-critical markets and SiFive Intelligence cores for vector processing workloads create a comprehensive IP portfolio for high-growth markets
  
  
• Codasip Teams Up with Western Digital to Support Adoption of Open-Source Processors (Tuesday Dec. 10, 2019)
  Codasip announced today that it has joined forces with Western Digital Corp. to become the preferred provider of hardware implementation packages and expert technical support for users of Western Digital’s SweRV Core EH1, a RISC-V core currently available to the open-source community and further supported by the open-source development organization CHIPS Alliance.
  
  
• Creonic Continues to Extend its Leading SATCOM IP Core Portfolio (Tuesday Dec. 10, 2019)
  Creonic GmbH, a leading IP core provider in the communications market, announced updates and improvements today, as well as new IP cores for satellite communications (SATCOM). The extensions complement the company’s SATCOM IP core portfolio, the broadest in the market.
  
  
• UltraSoC donates RISC-V trace implementation to enable true open-source development (Monday Dec. 09, 2019)
  UltraSoC today announced it will offer an open-source implementation of its industry-leading RISC-V trace encoder via the OpenHW Group.
  
  
• Andes 45-Series Expands RISC-V High-end Processors 8-Stage Superscalar Processor Balances High Performance, Power Efficiency, and Real-time Determinism with Rich RISC-V Ecosystem (Thursday Dec. 05, 2019)
  Andes Technology announces AndesCore™ 45-series CPU cores today. It is equipped with efficient superscalar pipeline to address a wide range of high-performance, power-sensitive and real-time embedded systems such as 5G, In-Vehicle Infotainment (IVI), Advanced Driver Assistance Systems (ADAS) and Solid State Disks (SSD).
  
  
• Mixel Announces Immediate Availability of MIPI D-PHY v2.5 IP (Tuesday Dec. 03, 2019)
  Mixel®, a leading provider of mixed-signal intellectual property (IP), announced today that its MIPI® D-PHY IP compliant to MIPI D-PHY v2.5 specification is now available. MIPI D-PHY supports MIPI Camera Serial Interface 2 (CSI-2), as well as Display Serial Interface (DSISM) and DSI-2.
  
  
• Think Silicon demonstrates early preview of Industry's first RISC-V ISA based 3D GPU at the RISC-V Summit (Tuesday Dec. 03, 2019)
  Think Silicon, recognized for the successful ultra-low power NEMA® GPU-Series for MCU driven SoCs, announced the demonstration of the industry’s first RISC-V ISA based 3D GPU -- the NEOX|V™.
  
  
• Imagination launches IMG A-Series: "The GPU of Everything" (Tuesday Dec. 03, 2019)
  Imagination Technologies announces the tenth generation of its PowerVR graphics architecture, the IMG A-Series. The fastest GPU IP ever released, IMG A-Series evolves the PowerVR GPU architecture to fulfil the graphics and compute needs of the full spectrum of next-generation devices.
  
  
• Silex Insight Introduces Video Codec IP using RAW input (CFA) (Tuesday Nov. 26, 2019)
  Silex Insight, a leading provider of video codec & AV over IP solutions, announces the extension of its codec family by introducing Video Codec IP (JPEG 2000/VC-2 HQ) using RAW input­ from Bayer filter (CFA).
  
  
• High-speed comms options enable in-life debug and optimization for datacenter, HPC and storage customers (Tuesday Nov. 19, 2019)
  UltraSoC today announced new high-speed communications capabilities within its embedded analytics architecture, supporting debug and performance optimization in datacenters, high-performance computing, AI and storage applications.
  
  
• Faraday and UMC Collaborate to Launch a Complete Set of 22nm Fundamental IP (Monday Nov. 18, 2019)
  Faraday Technology and United Microelectronics today announced the availability of Faraday's fundamental IP on UMC's 22nm ultra-low-power (ULP) and ultra-low-leakage (ULL) processes. The silicon-proven 22ULP/ULL fundamental IP, including multi-Vt standard cell libraries, ECO libraries, IO libraries, PowerSlash™ kit, and memory compilers, offers significant power reduction for the next level of SoC design.
  
  
• New Cadence UltraLink D2D PHY IP for Die-to-Die Connectivity Enables High-Performance Applications with Cost-Effective Packaging (Wednesday Nov. 13, 2019)
  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Cadence® UltraLink™ D2D PHY IP, a high-performance, low-latency PHY for die-to-die connectivity targeted at the AI/ML, 5G, cloud computing and networking market segments.
  
  
• Secure-IC and Andes Technology jointly provide cybersecurity enhanced RISC-V cores (Wednesday Nov. 13, 2019)
  Today, Secure-IC, the embedded security solutions provider from France specialized in embedded cybersecurity to protect against attacks, enters a strategic partnership with Andes Technology Corporation (TWSE: 6533), a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 1-billion diversified SoCs yearly.
  
  
• Rambus Announces Comprehensive PCI Express 5.0 Interface Solution (Wednesday Nov. 13, 2019)
  Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it now offers a comprehensive and optimized interface solution designed for PCI Express (PCIe) 5.0, with backward compatibility to PCIe 4.0, 3.0 and 2.0.
  
  
• Rianta Releases Ethernet MAC/PCS/FEC IP Suite for ASICs targeting Datacenter, Networking and 5G Mobile Infrastructure (Tuesday Nov. 12, 2019)
  Rianta Solutions announces new additions to its IP portfolio targeting ASIC and SoC devices. Rianta’s Ethernet IP packages serve 1G to 400G applications for Datacenter, Networking and 5G Wireless infrastructure.
  
  
• MediaTek Delivers 112G Long Range SerDes IP, Silicon-Proven on 7nm for ASIC Services (Monday Nov. 11, 2019)
  Available with silicon-proven 7nm FinFET process technology, MediaTek’s 112G LR SerDes enables data centers to quickly and efficiently process high volumes of specific types of data, accelerating the speed of computing.
  
  
• Arasan Announces MIPI D-PHY IP compliant to the latest MIPI D-PHY v2.1 Specifications for TSMC 16nm (Monday Nov. 11, 2019)
  Arasan Chip Systems a leading provider of semiconductor IP for mobile and automobile SoCs today announced the immediate availability of its MIPI D-PHY IP supporting the D-PHY v2.1 specification for speeds upto 4500 Mbps for TSMC 16nm SoC designs
  
  
• Announcing OpenTitan, the First Transparent Silicon Root of Trust (Wednesday Nov. 06, 2019)
  Today, we are excited to unveil the OpenTitan silicon root of trust (RoT) project, a new effort built using the successful collaborative engineering model created by lowRISC in partnership with Google and other commercial and academic partners.
  
  
• GLOBALFOUNDRIES and SiFive to Deliver Next Level of High Bandwidth Memory on 12LP Platform for AI Applications (Tuesday Nov. 05, 2019)
  GLOBALFOUNDRIES® (GF®) and SiFive, Inc. announced today at GLOBALFOUNDRIES Technology Conference (GTC) in Taiwan that they are working to extend high DRAM performance levels with High Bandwidth Memory (HBM2E) on GF’s recently announced 12LP+ FinFET solution, with 2.5D packaging design services to enable fast time-to-market for Artificial Intelligence (AI) applications.
  
  
• Arasan Announces MIPI D-PHY IP compliant to the latest MIPI D-PHY v2.1 Specifications (Monday Nov. 04, 2019)
  Arasan Chip Systems a leading provider of semiconductor IP for mobile and automobile SoCs today announced the immediate availability of its MIPI D-PHY IP supporting the D-PHY v2.1 specification for speeds upto 4500 Mbps for TSMC 12nm SoC designs
  
  
• OPENEDGES unveils high performance & low power GDDR6 controller IP (Monday Nov. 04, 2019)
  OPENEDGES Technology, Inc. the leading IP provider of Memory Subsystem IP today announced the release of GDDR6 memory controller IP.
  
  
• Rambus Achieves Industry-Leading GDDR6 Performance at 18 Gbps (Thursday Oct. 31, 2019)
  Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has achieved industry-leading 18 Gbps performance with the Rambus GDDR6 Memory PHY.
  
  
• Silex Insight Fast-track FIPS 140-2 Certification with NIST-Validated Crypto Coprocessor (Wednesday Oct. 30, 2019)
  Silex Insight, a leading provider for flexible security IP cores announced it has successfully validated their Crypto Coprocessor (BA450) through the NIST Cryptographic Algorithm Validation Program (CAVP).
  
  
• Synopsys Accelerates Cloud Computing SoC Designs with New Die-to-Die PHY IP in Advanced 7nm FinFET Process (Tuesday Oct. 29, 2019)
  Synopsys today announced its DesignWare® Die-to-Die PHY IP for ultra- and extra-short reach connectivity in multi-chip modules (MCM) for hyperscale data center, AI, and networking designs. The DesignWare Die-to-Die PHY IP supports NRZ and PAM-4 signaling from 2.5G to 112G data rates, delivering maximum throughput per die edge for large MCM designs.
  
  
• Sofics Analog I/O's and ESD clamps proven for TSMC 16nm, 12nm and 7nm FinFET processes (Monday Oct. 28, 2019)
  Sofics bvba, a leading semiconductor integrated circuit IP provider announced that its TakeCharge® Electrostatic Discharge (ESD) portfolio is silicon proven on TSMC’s advanced 16nm, 12nm and 7nm FinFET processes.
  
  
• SiFive Announces New U8-Series Core IP For High-Performance Compute (Monday Oct. 28, 2019)
  SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, announced today a portfolio of new, high-performance IP for scalable SoC Designs.
  
  
• Innosilicon's Broad IP Portfolio Qualified on GLOBALFOUNDRIES 12LP FinFET Platform for High-Performance Applications (Thursday Oct. 24, 2019)
  Innosilicon announced today that its comprehensive IP portfolio has been qualified on GLOBALFOUNDRIES® (GF ®) 12nm Leading-Performance (12LP) platform