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IP / SOC Products News

• StreamDSP Announces Major Update to 17.3 IP Core (Wednesday Jul. 17, 2019)
  StreamDSP announces immediate availability of version 1.8 of the VITA 17.3 (sFPDP Gen 3) IP core. The latest v1.8 release contains support for most of the popular FPGA device families from Intel, Altera, and Xilinx.
  
  
• Alphawave IP Announces Immediate Availability of Advanced PCIe Gen1-5 PHY on TSMC's 7nm process (Tuesday Jul. 16, 2019)
  Alphawave IP today announced immediate availability of its PipeCORE® PCIe Gen1-5 PHY. PipeCORE® is an advanced DSP based 7nm PCIe Gen1-5 PHY and is available on TSMC’s industry-leading 7nm process technology.
  
  
• New IP catalog from Terminus Circuits (Tuesday Jul. 16, 2019)
  This IP portfolio includes PCIe Gen4 with backward compatibility, USB 3.2 Gen 2x2 and its variants, MIPI M-Phy G4 with backward compatibility, PLL's (RO & LC) upto 16GHz with Spread Spectrum Clocking Generation, Reference clock PLL subsystems for PCIe, USB, MIPI Mphy, Ethernet SerDes, PVT compensated Resistor Termination, Current & Voltage bias circuitry.
  
  
• CFX announces commercial availability of anti-fuse OTP technology on SMIC 55HV process (Friday Jul. 12, 2019)
  CFX, the One-Stop Shop for nonvolatile memory technology and products announced today commercial availability of anti-fuse OTP technology on SMIC 55HV process.
  
  
• InAccel releases open-source Logistic Regression IP core for FPGAs (Monday Jul. 08, 2019)
  InAccel has released today as open-source the FPGA IP core for the training of logistic regression algorithms. The accelerated FPGA IP core offers up to 70x speedup compared to a single threaded execution and up to 12x compared to an 8-core general purpose CPU execution respectively.
  
  
• AGIC Tape Out First Silicon at 14nm FinFET Technology (Thursday Jul. 04, 2019)
  AGIC C-Fuse OTP has been taped out on the foundry’s 14nm technology platform on June 20th. In addition, AGIC will have a bunch of tape out events from 180nm to 22nm platform in Tier 1 foundries later 2019.
  
  
• Vidatronic Announces New Silicon-Proven Power Management Unit Intellectual Property Core for Samsung Foundry (Tuesday Jul. 02, 2019)
  Vidatronic today announced the release of the latest addition to their Power Quencher® series, the VLDS0300LS130, a low dropout (LDO) voltage regulator IP core optimized for battery-powered devices where low power is critical.
  
  
• PLDA Reaches Key Milestone in Gen-Z IP Development (Monday Jul. 01, 2019)
  In support of immediate Gen-Z development, PLDA has released a detailed datasheet enabling designers to begin architecting and designing Gen-Z enabled SoCs. This PLDA Gen-Z IP datasheet includes the key information required for initial design including supporting features, interface description and micro architecture, gate count, performance metrics, and more.
  
  
• Rambus Expands Family of CryptoManager Root of Trust Secure Silicon IP Cores (Thursday Jun. 27, 2019)
  Rambus today announced the expansion of the CryptoManager Root of Trust family of products, a series of fully programmable, hardware-level secure silicon IP cores to address the security needs of applications including IoT, AI, ML, cloud, government, military and automotive. CryptoManager cores employ a siloed architecture.
  
  
• eMemory's NeoFuse Qualified on Winbond 25nm DRAM Process (Tuesday Jun. 25, 2019)
  eMemory today announced that NeoFuse, its one-time programmable (OTP) non-volatile memory IP, has been qualified on Winbond 25nm DRAM process technology and ready for production.
  
  
• CSEM and MIFS demonstrate world-record lows in energy consumption for a microcontroller (Wednesday Jun. 19, 2019)
  Combining CSEM’s ultra-low-power ASIC design experience with the Extreme-Low Power (ELP) DDC technology from MIFS enables new world records in power consumption. A complete process design kit, along with a range of mixed-signal silicon IPs, is now available.
  
  
• X-FAB and Efabless Announce Successful First Silicon of Raven, An Open-Source RISC-V Microcontroller (Thursday Jun. 13, 2019)
  X-FAB Silicon Foundries, the leading analog/mixed-signal and specialty foundry, together with crowd-sourcing IC platform partner Efabless Corporation, today announced the successful first-silicon availability of the Efabless RISC-V System on Chip (SoC) reference design.
  
  
• Logic Design Solutions Introduces the first NVMe Host IP on PolarFire FPGA (Tuesday Jun. 11, 2019)
  Logic Design Solutions (LDS) extends its portfolio of NVME-HOST IPs with the first NVME-HOST IP on POLARFIRE FPGA which enables designers to address specific market in embedded recording domain.
  
  
• Andes Technology Launches RISC-V FreeStart Program with its Commercial-Grade CPU N22 (Monday Jun. 10, 2019)
  Andes Technology today announces its RISC-V FreeStart program. The program offers an easy and fast way to build a solid SoC foundation on the commercial-grade RISC-V CPU core N22, available for free download. AndesCore™ N22 is an entry-level, ultra-compact, low-power and performance-efficient RISC-V CPU IP.
  
  
• CEVA Collaborates with Ellisys to Achieve SIG Qualification for its Bluetooth 5.1 Low Energy IP (Monday Jun. 10, 2019)
  CEVA today announced that it has completed qualification testing of its RivieraWaves Bluetooth 5.1 Low Energy IP using the Ellisys Bluetooth Qualifier™ (EBQ) compliance tester.
  
  
• SingMai offer universal encoding and decoding of analogue video (Monday Jun. 10, 2019)
  SingMai have added SECAM encoding and decoding to their PT8 and PT5 IP cores. By doing so SingMai’s analogue encoding and decoding IP portfolio can decode all standard and high definition analogue video formats.
  
  
• Synopsys and GLOBALFOUNDRIES Collaborate to Develop Broad Portfolio of DesignWare IP for 12LP FinFET Process (Tuesday Jun. 04, 2019)
  Synopsys today announced its collaboration with GLOBALFOUNDRIES (GF) to develop a broad portfolio of DesignWare® IP, including Multi-Protocol 25G, USB 3.0 and 2.0, PCI Express® 2.0, DDR4, LPDDR4/4X, MIPI D-PHY, SD-eMMC, and Data Converters, for GF's 12-nanometer (nm) Leading-Performance (12LP) FinFET process technology.
  
  
• Analog Bits and GLOBALFOUNDRIES Deliver Differentiated Analog and Mixed Signal IP for High-Performance Mobile and Compute Applications (Tuesday Jun. 04, 2019)
  Analog Bits and GLOBALFOUNDRIES (GF) today announced the availability of Analog Bits analog and mixed signal IP design kits for GF’s 12nm Leading-Performance (12LP) process technology.
  
  
• Gyrfalcon offers Automotive AI Chip Technology (Monday Jun. 03, 2019)
  IP Licensing for Matrix Based AI Accelerator that Optimizes Performance with Low Energy for Self-Driving and Automotive AI Functions
  
  
• BrainChip Announces the Availability of Advanced AI Intellectual Property (Wednesday May. 29, 2019)
  BrainChip today announced the availability of the Company’s Akida Neural Processing Core (“NPC”) as intellectual property available for licensing. This introduction marks a major development in the Company’s market presence.
  
  
• Delivering next-generation AI experiences for the 5G world (Monday May. 27, 2019)
  Over the past 12+ months here at Arm we have delivered several new solutions which scale from the edge of the network to the cloud. These include Arm’s Project Trillium, Arm® Neoverse™, two new Automotive Enhanced processors with new safety features, and our Pelion IoT platform for securely managing IoT devices.
  
  
• CAST Expands Popular UDP/IP Networking Cores Line (Thursday May. 23, 2019)
  CAST, Inc. today announced two extensions to its line of UDP/IP cores for lean Internet Protocol networking: an increase up to 32 channels for its existing 10G and 40G UDP/IP Hardware Protocol Stacks, and the upcoming release of a faster, 100G version of these IP cores.
  
  
• AnalogX Launches Ultra Low Power Interconnect SerDes IP Portfolio to Fuel Next-Generation I/O Connectivity (Thursday May. 23, 2019)
  AnalogX Inc., a Canadian corporation, is delighted to unveil its new, silicon-proven, multi-protocol, 1 to 33Gbps AXLinkIO connectivity IP portfolio. The AXLinkIO portfolio of Serializer/Deserializer interconnect IP solutions is ideally suited for high-bandwidth chiplets and chips in AI processors, 5G networking, optical interfaces, and datacenter computing.
  
  
• AGIC Technology to Achieve In-Memory Computing for AI Edge Computation (Thursday May. 23, 2019)
  In-Memory Computation (IMC) is an emerge architecture for recent AI deep learning filed. Different from traditional computing, IMC could process data in parallel and shorter processing time. In AI neural network system, the weighting is calculated by resistance changing of memory.
  
  
• Arasan announces the immediate availability of its MIPI CSI-2 v2.1 IP supporting C-PHY v1.2 and D-PHY v2.1 (Wednesday May. 22, 2019)
  Arasan Chip Systems announces the immediate availability its MIPI CSI-2 v2.1 Tx and Rx IP Cores seamlessly integrated with its MIPI C-PHY v.1.2 IP supporting speeds of upto 3.5gsps and D-PHY v2.1 supporting speeds of upto 4.5gbps.
  
  
• Arteris IP and Wave Computing Collaborate on Reference Architecture for Enterprise Dataflow Platform (Tuesday May. 21, 2019)
  Arteris IP and Wave Computing are collaborating to create a blueprint that can help customers overcome compute-to-memory design challenges. Additionally, Wave Computing is licensing Arteris IP’s Ncore Cache Coherent Interconnect, FlexNoC interconnect IP, and its accompanying FlexNoC AI Package for use in the AI-enabled chips that fuel Wave Computing’s data center systems products.
  
  
• Making virtual more of a reality with the new Arm Mali-D77 display processor (Wednesday May. 15, 2019)
  Enabling VR to be a common part of the user experience on billions of devices worldwide is the long-term goal. Arm is meeting the challenge with the all new Arm® Mali™-D77 display processing unit (DPU) which will take VR to the next level by tackling display challenges head-on.
  
  
• New Cadence Tensilica Vision Q7 DSP IP Doubles Vision and AI Performance for Automotive, AR/VR, Mobile and Surveillance Markets (Wednesday May. 15, 2019)
  Cadence today expanded the high end of its popular Tensilica® Vision DSP product family with the introduction of the Cadence® Tensilica Vision Q7 DSP delivering up to 1.82 tera operations per second (TOPS).
  
  
• eSilicon Announces Production Qualification of 5G Infrastructure ASIC (Wednesday May. 15, 2019)
  eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today that a large 2.5D FinFET ASIC targeting the 5G infrastructure market is entering final product qualification.
  
  
• Cadence Announces Broad Next-Generation Memory Standard Support in Samsung Foundry's Advanced Process Technologies (Wednesday May. 15, 2019)
  Cadence has taped out DDR5/4 PHY IP on the Samsung 7nm Low Power Plus (7LPP) process, GDDR6 PHY IP on the Samsung 14nm Low Power Plus (14LPP) process and 2.4G High-Bandwidth Memory 2 (HBM2) PHY IP on the Samsung 10nm Low Power Plus (10LPP) process, which has been recharacterized as the 8nm Low Power Plus (8LPP) process.