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IP / SOC Products News

• Synopsys Targets 400G Hyperscale Data Centers with High-Performance Ethernet IP (Tuesday Jul. 24, 2018)
  Synopsys, Inc. (Nasdaq: SNPS) today announced the new DesignWare® 56G Ethernet PHY IP for emerging 400 gigabit-per-second (Gbps) hyperscale data center system-on-chips (SoCs). The advanced 56G Ethernet PHY architecture incorporates Synopsys' silicon-proven data converters with a configurable transmitter and digital signal processor (DSP)-based receiver to deliver the best power and performance tradeoffs for the target application.
  
  
• Microsemi PolarFire FPGAs Enable Smallest, Lowest Power DisplayPort Implementations with New IP from Bitec (Tuesday Jul. 24, 2018)
  Microsemi Corporation today announced the availability of Bitec's DisplayPort™ intellectual property (IP) core optimized for PolarFire™ field programmable gate arrays (FPGAs).
  
  
• Silex Inside eSecure Root-of-Trust Security IP Is Excellent Fit with RISC-V Cores (Friday Jul. 06, 2018)
  Silex Inside announces that its comprehensive eSecure IP solution is also available for RISC-V architectures. eSecure is a silicon proven IP module that turns ASIC, FPGA or SoC designs into fully secured applications that guarantee the authenticity and integrity of the hardware, software, data, and communication.
  
  
• Silex Inside releases a secure connection engine (Tuesday Jul. 03, 2018)
  The newly released BA452 is a secure connection engine that can be used to off-load the compute intensive Public Key operations (Diffie-Helmann, Signature Generation and Verification).
  
  
• CAST Releases TSN Ethernet Subsystem for Automotive and Industrial Applications (Monday Jul. 02, 2018)
  Semiconductor intellectual property provider CAST, Inc. concluded Design Automation Conference (DAC) week by announcing the only available IP subsystem implementing the latest IEEE standards for Time Sensitive Networking (TSN) over Ethernet.
  
  
• Flex Logix EFLX4K IO eFPGA Core Enables Very Wide Bus Connections for Networking Applications (Tuesday Jun. 26, 2018)
  Flex Logix Technologies, Inc.the leading supplier of embedded FPGA (eFPGA) IP, architecture and software, announced today a new member of the EFLX4K eFPGA Core Family: the EFLX4K IO eFPGA core.
  
  
• 7nm networking platform delivers unprecedented performance and configurability for data center ASICs (Tuesday Jun. 26, 2018)
  eSilicon, an independent provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the availability of a complete, highly configurable 7nm IP platform targeted for networking and data center applications.
  
  
• General Processor Technologies Announces AI Accelerator and DSP for Digital and Image Processing (Tuesday Jun. 26, 2018)
  General Processor Technologies (GPT), China's leading licensor of customizable processor IP cores, announced two innovative new additions to its IP portfolio: the 'GPT' AI accelerator and the VLVm1 Digital Signal Processor (DSP) for digital and image processing.
  
  
• Spectral releases Silicon proven High Speed Low Power SRAM compilers in the 40/45nm CMOS/RFSOI process nodes targeted for a wide range of IOT & 5G Applications (Tuesday Jun. 26, 2018)
  Spectral Design & Test Inc. (SDT) today announced that their lead customers are integrating dozens of configurations of SRAM & Register File macros generated by Memory compilers developed in 40/45nm bulk CMOS & RFSOI nodes across multiple foundries.
  
  
• NetSpeed launches SoCBuilder - AI-powered design and integration platform to accelerate SoC designs (Monday Jun. 25, 2018)
  NetSpeed Systems today announced the release of its SoCBuilder, an AI-powered SoC design and integration platform. SoCBuilder includes a catalog of pre-integrated third-party IP along with application-specific reference designs for AI, Automotive, 5G, hyperscale compute and AR/VR.
  
  
• Flex Logix Improves Deep Learning Performance By 10X With New EFLX4K AI eFPGA Core (Monday Jun. 25, 2018)
  Flex Logix® Technologies, Inc., the leading supplier of embedded FPGA (eFPGA) IP, architecture and software, announced today a new member of the EFLX4K eFPGA Core Family: the EFLX4K Artificial Intelligence (AI) eFPGA core.
  
  
• Moortec Supporting Today's Connectivity Boom with IoT Specific Embedded In-Chip Monitoring Subsystem Solution (Monday Jun. 25, 2018)
  Moortec, the in-chip sensing solutions provider, are pleased to announce the availability of a smaller scale, lower power, Internet-of-Things (IoT) focused embedded monitoring subsystem, targeting TSMC’s 40ULP (Ultra Low Power) process technology.
  
  
• CEVA Extends its Leadership in NB-IoT IP with CEVA-Dragonfly NB2, the World's First eNB-IoT Rel14 Solution (Monday Jun. 25, 2018)
  CEVA-Dragonfly NB2 is a highly-integrated and modular solution optimized for Cat-NB2 (3GPP Release 14 eNB-IoT) that can seamlessly be incorporated into chips and modules by the multitude of companies looking to address the large and fast-growing cellular IoT space.
  
  
• Sankalp Semiconductor announces release of its eDP receiver IP for Chip on Glass Applications (Monday Jun. 25, 2018)
  Sankalp Semiconductor a design service company offering comprehensive digital & mixed signal SoC solutions today at 55th DAC 2018 announced release of its Embedded DisplayPort (eDP) receiver IP. DisplayPort offers high bandwidth, lower pin count and low power solutions for high-resolution displays.
  
  
• Gidel Launches Lossless Compression IP that Reduces Storage Needs by Over 50%, Utilizing Only 1% of the FPGA, with Low Power Consumption (Monday Jun. 25, 2018)
  Gidel, a technology leader in highperformance accelerators utilizing FPGAs, today announced a new compression IP and a renewed focus on compression and encryption algorithms for the HPC and Vision markets.
  
  
• SiFive Unveils E2 Core IP Series for Smallest, Lowest Power RISC-V Designs (Monday Jun. 25, 2018)
  SiFive, the leading provider of commercial RISC-V processor IP, today announced the availability of its E2 Core IP Series, configurable low-area, low-power microcontroller (MCU) cores designed for use in embedded devices.
  
  
• Arm and Samsung Foundry push the possibilities of semiconductor manufacturing (Friday Jun. 22, 2018)
  Arm and Samsung Foundry push the possibilities of semiconductor manufacturing with industry’s first eMRAM compiler and new physical IP offerings on advanced process nodes including 7nm and 5nm
  
  
• NetSpeed unveils Orion AI - Delivering extreme performance and ultimate efficiency for next-gen AI SoCs (Thursday Jun. 21, 2018)
  NetSpeed Systems today announced the release of Orion AI, the industry’s first SoC interconnect solution targeted specifically for AI-enable SoC applications. It includes advanced features such as multicast and broadcast to improve performance and efficiency in AI-enable SoCs and accelerator ASICs used for datacenters, autonomous vehicles, AR/VR, and advanced video analytics.
  
  
• Flex Logix EFLX1K eFPGA Cores Enable Array-Efficient Reconfigurable Logic on 40nm to 180nm Nodes (Tuesday Jun. 19, 2018)
  Flex Logix Technologies, Inc., the leading supplier of embedded FPGA (eFPGA) IP, architecture and software, announced today a new EFLX eFPGA core optimized for the needs of customers on 40nm to 180nm nodes.
  
  
• Arasan Announces SD Card UHS-II PHY IP for 12nm SoC Designs (Tuesday Jun. 19, 2018)
  Arasan today announced the immediate availability of its SD Card UHS-II PHY for 12nm SoC designs compliant to the latest 4.1 Specification supporting speeds of up to 3.12 Gbps.
  
  
• Chips&Media launches HEVC/H.264 combined codec IP (Single Core) optimized for UHD (4K, 60 FPS) (Wednesday Jun. 13, 2018)
  Chips&Media, Inc. a leading video IP company headquartered in Seoul, Korea, announced the introduction of WAVE521C, a new codec IP with single core based integrated HEVC and H.264.
  
  
• CAST Adds JPEG-LS Decoder to Lossless Image Compression IP Core Suite (Tuesday Jun. 12, 2018)
  Semiconductor intellectual property provider CAST, Inc. has released a JPEG-LS Decoder IP core that—together with the JPEG-LS Encoder already available—provides an efficient hardware compression solution for the lossless or near-lossless transmission or storage of high quality images or video sequences.
  
  
• MIPS I6500-F First High Performance 64 Bit Multi-Cluster CPU IP to Receive ISO 26262 and LEC 61508 Certification (Monday Jun. 11, 2018)
  MIPS today announced that its I6500-F CPU IP core, designed as a Safety Element out of Context (SEooC), is the first high performance 64 bit multi-cluster CPU IP to receive formal certification of compliance for ASIL B [D], based on ISO 26262: 1st edition 2011 (&DIS 2nd Edition 2018) and IEC 61508 SIL 2.
  
  
• PowerVR Series2NX neural network accelerator cores set the standard for performance and cost-efficiency (Friday Jun. 08, 2018)
  Imagination Technologies announces two neural network cores, the AX2185 and AX2145, designed to enable high-performance computation of neural networks at very low power consumption in minimal silicon area.
  
  
• Arteris IP Announces CodaCache Standalone Last Level Cache (Thursday Jun. 07, 2018)
  Arteris IP today announced the CodaCache standalone last level cache (LLC) for high-performance systems-on-chip (SoCs). The Arteris IP CodaCache LLC is highly configurable and offers system-wide performance improvements and power savings while providing seamless integration into SoCs with Arm® AMBA® AXI interfaces.
  
  
• Mobiveil and Avery Design Systems Partner to Provide SoC Designers a Fully Verified and Compliant PCIe 5.0 IP Solution (Wednesday Jun. 06, 2018)
  Mobiveil, Inc. today announced that it is partnering with Avery Design Systems to deliver a complete PCIe 5.0 IP solution for SoC designers needing a fully verified and compliant PCIe 5.0 interface solution for their designs.
  
  
• eSilicon revolutionizes machine learning ASIC platform (MLAP) market (Tuesday Jun. 05, 2018)
  eSilicon announced today at the Machine Learning and AI Developer’s Conference a fundamentally new approach to building application-specific integrated circuits (ASICs) for artificial intelligence (AI)/neural network applications called the neuASIC platform.
  
  
• IP Cores, Inc. Announces Modifications of the 400 Gbps MACsec IP Cores (Monday Jun. 04, 2018)
  IP Cores, Inc., (California, USA, http://www.ipcores.com) has announced modifications of its MSP10-512 cores that support line-speed MACsec encryption and decryption for the 400 Gbps Ethernet.
  
  
• PLDA Announces Availability of XpressRICH5 PCIe 5.0 Controller IP (Monday Jun. 04, 2018)
  PLDA today announced availability of their XpressRICH5™ PCIe® 5.0 Controller IP. PLDA’s XpressRICH5 supports rev. 0.7 of the PCIe 5.0 Specification and is available for ASIC, SoC and FPGA implementation, allowing early adopters to seamlessly improve their link throughtput to 32 GT/s per lane and reduce their overall latency.
  
  
• Arm announces new suite of IP for premium mobile experiences (Friday Jun. 01, 2018)
  For Small Screens to Large: Introducing a New Suite of IP for Premium Mobile Experiences